MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 377

• Manufacturer Part Number: MMC2107CFCPV33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCPV33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

MMC2107 – Rev. 2.0
MOTOROLA
NOTE:
NOTE:
MSTR — Master Bit
CPOL — Clock Polarity Bit
CPHA — Clock Phase Bit
SSOE — Slave Select Output Enable Bit
Setting the SSOE bit disables the mode fault detect function.
LSBFE — LSB-First Enable Bit
In SPIDR, the MSB is always bit 7 regardless of the LSBFE bit.
The MSTR bit selects SPI master mode or SPI slave mode operation.
Reset clears MSTR.
The CPOL bit selects an inverted or non-inverted SPI clock. To
transmit data between SPI modules, the SPI modules must have
identical CPOL values. Reset clears CPOL.
The CPHA bit delays the first edge of the SCK clock. Reset sets
CPHA.
The SSOE bit and the DDRSP3 bit configure the SS pin as a
general-purpose input or a slave-select output. Reset clears SSOE.
The LSBFE enables data to be transmitted LSB first. Reset clears
LSBFE.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Master mode
0 = Slave mode
1 = Active-low clock; SCK idles high
0 = Active-high clock; SCK idles low
1 = First SCK edge at start of transmission
0 = First SCK edge 1/2 cycle after start of transmission
1 = Data transmitted LSB first.
0 = Data transmitted MSB first
Serial Peripheral Interface Module (SPI)
DDRSP3 SSOE
0
0
1
1
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Table 17-3. SS Pin I/O Configurations
0
1
0
1
Mode-fault input
General-purpose input
General-purpose output
Slave-select output
Master Mode
Serial Peripheral Interface Module (SPI)
Memory Map and Registers
Slave-select input
Slave-select input
Slave-select input
Slave-select input
Slave Mode
Technical Data
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