MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 381

no-image

MMC2107CFCPV33

Manufacturer Part Number
MMC2107CFCPV33
Description
IC MCU 33MHZ 128K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Datasheet

Specifications of MMC2107CFCPV33

Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
32
Number Of Timers
4 bit
Operating Supply Voltage
0 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MMC2107CFCPV33
Manufacturer:
AMD
Quantity:
1 001
Part Number:
MMC2107CFCPV33
Manufacturer:
MOTOLOLA
Quantity:
745
Part Number:
MMC2107CFCPV33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MMC2107CFCPV33
Manufacturer:
MOT
Quantity:
2
Part Number:
MMC2107CFCPV33
Manufacturer:
FREESCALE
Quantity:
20 000
17.7.4 SPI Status Register
MMC2107 – Rev. 2.0
MOTOROLA
Address: 0x00cb_0003
Reset:
Read: Anytime
Write: Has no meaning or effect
SPIF — SPI Interrupt Flag
WCOL — Write Collision Flag
MODF — Mode Fault Flag
Read:
Write:
The SPIF flag is set after the eighth SCK cycle in a transmission when
received data transfers from the shift register to SPIDR. If the SPIE bit
is also set, SPIF generates an interrupt request. Once SPIF is set, no
new data can be transferred into SPIDR until SPIF is cleared. Clear
SPIF by reading SPISR with SPIF set and then accessing SPIDR.
Reset clears SPIF.
The WCOL flag is set when software writes to SPIDR during a
transmission. Clear WCOL by reading SPISR with WCOL set and
then accessing SPIDR. Reset clears WCOL.
The MODF flag is set when the SS pin of a master SPI is driven low
and the SS pin is configured as a mode-fault input. If the SPIE bit is
also set, MODF generates an interrupt request. A mode fault clears
the SPE, MSTR, and DDRSP[2:0] bits. Clear MODF by reading
SPISR with MODF set and then writing to SPICR1. Reset clears
MODF.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = New data available in SPIDR
0 = No new data available in SPIDR
1 = Write collision
0 = No write collision
1 = Mode fault
0 = No mode fault
Serial Peripheral Interface Module (SPI)
SPIF
Bit 7
0
Go to: www.freescale.com
Figure 17-5. SPI Status Register (SPISR)
= Writes have no effect and the access terminates without a transfer error exception.
WCOL
6
0
5
0
0
MODF
4
0
Serial Peripheral Interface Module (SPI)
3
0
0
Memory Map and Registers
2
0
0
1
0
0
Technical Data
Bit 0
0
0
381

Related parts for MMC2107CFCPV33