MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 417

• Manufacturer Part Number: MMC2107CFCPV33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCPV33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

MMC2107 – Rev. 2.0
MOTOROLA
TRG — Trigger Assignment Bit
PSH[8:4] — Prescaler Clock High Time Field
The TRG bit allows the software to assign the ETRIG[2:1] pins to
queue 1 and queue 2.
The PSH field selects the QCLK high time in the prescaler.
See
clock frequency (f
range, the PSH field selects the high time of the QCLK, which can
range from 1 to 32 system clock cycles. The minimum high time for
the QCLK is specified as t
which enable a range of QCLK high times.
Freescale Semiconductor, Inc.
PSH[8:4]
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
1 = ETRIG1 triggers queue 2, ETRIG2 triggers queue 1
0 = ETRIG1 triggers queue 1, ETRIG2 triggers queue 2
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
Section 22. Electrical Specifications
Go to: www.freescale.com
10 system clock cycles
11 system clock cycles
12 system clock cycles
13 system clock cycles
14 system clock cycles
15 system clock cycles
16 system clock cycles
2 system clock cycles
3 system clock cycles
4 system clock cycles
5 system clock cycles
6 system clock cycles
7 system clock cycles
8 system clock cycles
9 system clock cycles
1 system clock cycle
Table 18-3. Prescaler Clock High Times
QCLK High Time
QCLK
) values. To keep the QCLK within the specified
PSH
.
Table 18-3
Queued Analog-to-Digital Converter (QADC)
PSH[8:4]
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
displays the bits in PSH field
for operating
17 system clock cycles
18 system clock cycles
19 system clock cycles
20 system clock cycles
21 system clock cycles
22 system clock cycles
23 system clock cycles
24 system clock cycles
25 system clock cycles
26 system clock cycles
27 system clock cycles
28 system clock cycles
29 system clock cycles
30 system clock cycles
31 system clock cycles
32 system clock cycles
QCLK High Time
Register Descriptions
Technical Data
417