MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 428

• Manufacturer Part Number: MMC2107CFCPV33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCPV33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Queued Analog-to-Digital Converter (QADC)
Technical Data
428
PF1 — Queue 1 Pause Flag
The end-of-queue 1 is identified when execution is complete on the
CCW in the location prior to that pointed to by BQ2, when the current
CCW contains an end-of-queue code instead of a valid channel
number, or when the currently completed CCW is in the last location
of the CCW RAM.
When CF1 is set and interrupts are enabled for that queue completion
flag, the QADC asserts an interrupt request. The software reads the
completion flag during an interrupt service routine to identify the
interrupt request. The interrupt request is cleared when the software
writes a 0 to the completion flag bit, when the bit was previously read
as a 1. Once set, only software or reset can clear CF1.
CF1 is maintained by the QADC regardless of whether the
corresponding interrupt is enabled. The software polls for CF1 bit to
see if it is set. This allows the software to recognize that the QADC is
finished with a queue 1 scan. The software acknowledges that it has
detected the completion flag being set by writing a 0 to the completion
flag after the bit was read as a 1.
PF1 indicates that a queue 1 scan has reached a pause. PF1 is set
by the QADC when the current queue 1 CCW has the pause bit set,
the selected input channel has been converted, and the result has
been stored in the result table.
Once PF1 is set, the queue enters the paused state and waits for a
trigger event to allow queue execution to continue. However, if the
CCW with the pause bit set is the last CCW in a queue, the queue
execution is complete. The queue status becomes idle, not paused,
and both the pause and completion flags are set. Another exception
occurs in software controlled mode, where the PF1 can be set but
queue 1 never enters the pause state since queue 1 continues without
pausing.
When PF1 is set and interrupts are enabled for the corresponding
queue, the QADC asserts an interrupt request. The software may
read PF1 during an interrupt service routine to identify the interrupt
request. The interrupt request is cleared when the software writes a 0
to PF1, when the bit was previously read as a 1. Once set, only
software or reset can clear PF1.
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
Go to: www.freescale.com
MMC2107 – Rev. 2.0
MOTOROLA