MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 453

• Manufacturer Part Number: MMC2107CFCPV33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCPV33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

18.10.1.2 Queue Priority Schemes
MMC2107 – Rev. 2.0
MOTOROLA
NOTE:
CCW is executed sequentially until the last CCW in the subqueue is
executed and the pause state is entered. Execution can only continue
with the next CCW, which is the beginning of the next subqueue. A
subqueue cannot be executed a second time before the overall queue
execution has been completed.
Trigger events which occur during the execution of a subqueue are
ignored, except that the trigger overrun flag is set. When a
continuous-scan mode is selected, a trigger event occurring after the
completion of the last subqueue (after the queue completion flag is set),
causes the execution to continue with the first subqueue, starting with
the first CCW in the queue.
When the QADC encounters a CCW with the pause bit set, the queue
enters the paused state after completing the conversion specified in the
CCW with the pause bit. The pause flag is set and a pause software
interrupt may optionally be issued. The status of the queue is shown to
be paused, indicating completion of a subqueue. The QADC then waits
for another trigger event to again begin execution of the next subqueue.
Since there are two conversion command queues and only one A/D
converter, there is a priority scheme to determine which conversion is to
occur. Each queue has a variety of trigger events that are intended to
initiate conversions, and they can occur asynchronously in relation to
each other and other conversions in progress. For example, a queue can
be idle awaiting a trigger event, a trigger event can have occurred, but
the first conversion has not started, a conversion can be in progress, a
pause condition can exist awaiting another trigger event to continue the
queue, and so on.
The following paragraphs and figures outline the prioritizing criteria used
to determine which conversion occurs in each overlap situation.
Each situation in
through S19. In each diagram, time is shown increasing from left to right.
The execution of queue 1 and queue 2 (Q1 and Q2) is shown as a string
of rectangles representing the execution time of each CCW in the queue.
In most of the situations, there are four CCWs (labeled C1 to C4) in both
queue 1 and queue 2. In some of the situations, CCW C2 is presumed
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
Go to: www.freescale.com
Figure 18-23
through
Queued Analog-to-Digital Converter (QADC)
Figure 18-33
are labeled S1
Technical Data
Digital Control
453