MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 461

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MMC2107CFCPV33

Manufacturer Part Number
MMC2107CFCPV33
Description
IC MCU 33MHZ 128K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Datasheet

Specifications of MMC2107CFCPV33

Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
32
Number Of Timers
4 bit
Operating Supply Voltage
0 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available

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MMC2107 – Rev. 2.0
MOTOROLA
QS
Q1
Q2
QS
Q1
Q2
0000
0000
IDLE
IDLE
Q2:
Q2:
IDLE
IDLE
T2
T2
C1
C1
ACTIVE
ACTIVE
0010
0010
Situations S10 and S11
when an additional trigger event is detected for queue 2 while the queue
is suspended, the trigger overrun error bit is set, the same as if queue 2
were being executed when a new trigger event occurs. Trigger overrun
on queue 2 thus permits the software to know that queue 1 is taking up
so much QADC time that queue 2 trigger events are being lost.
C2
C2
Q1:
Q1:
Figure 18-32. CCW Priority Situation 10
Figure 18-33. CCW Priority Situation 11
Freescale Semiconductor, Inc.
T1
T1
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
TOR2
TOR2
C1
C1
SUSPEND
SUSPEND
ACTIVE
ACTIVE
T2
T2
1010
1010
C2
C2
Go to: www.freescale.com
PF1
PF1
0110
ACT
C1
C2
ACTIVE
0110
PF2
PAUSE
0101
C2
PAUSE
PAUSE
PF2
T2
PAUSE
0101
(Figure 18-32
C3
ACTIVE
0110
T2
0110
ACT
C3
C4
T1
T1
TOR2
TOR2
C3
Queued Analog-to-Digital Converter (QADC)
SUSPEND
C3
SUSPEND
ACTIVE
ACTIVE
T2
T2
1010
1010
C4
C4
and
CF1
CF1
ACT
0010
C3
Figure
C4
ACTIVE
0010
CF2
C4
RESUME = 1
CF2
18-33) show that
IDLE
IDLE
RESUME = 0
IDLE
0000
IDLE
0000
Technical Data
Digital Control
461

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