MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 479

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MMC2107CFCPV33

Manufacturer Part Number
MMC2107CFCPV33
Description
IC MCU 33MHZ 128K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Datasheet

Specifications of MMC2107CFCPV33

Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
32
Number Of Timers
4 bit
Operating Supply Voltage
0 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available

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MMC2107 – Rev. 2.0
MOTOROLA
CLOCK (f
EXAMPLE 1
EXAMPLE 2
SYSTEM
QCLK
QCLK
sys
)
NOTE:
Figure 18-43. QADC Clock Programmability Examples
Figure 18-43
programmability. The examples include conversion times based on this
assumption:
Figure 18-43
for a single conversion in a queue. For other MCU system clock
frequencies and other input sample times, the same calculations can be
made.
PSA is maintained for software compatibility but has no functional
benefit to this version of the module.
The MCU system clock frequency is the basis of the QADC timing. The
QADC requires that the system clock frequency be at least twice the
QCLK frequency. The QCLK frequency is established by the
combination of the PSH and PSL parameters in QACR0. The 5-bit PSH
field selects the number of system clock cycles in the high phase of the
QCLK wave. The 3-bit PSL field selects the number of system clock
cycles in the low phase of the QCLK wave.
Example Number
Input sample time is as fast as possible (IST = 0, 2 QCLK cycles).
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
Control Register 0 Information
1
2
Go to: www.freescale.com
Table 18-15. QADC Clock Programmability
and
and
Table 18-15
Table 18-15
Frequency
40 MHz
32 MHz
20 CYCLES
also show the conversion time calculated
show examples of QCLK
PSH
Queued Analog-to-Digital Converter (QADC)
11
7
PSL
7
7
QCLK
(MHz)
2.0
2.0
Input Sample Time
IST = Binary 00
Conversion Time
Technical Data
Digital Control
( s)
7.0
7.0
479

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