MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 483

• Manufacturer Part Number: MMC2107CFCPV33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCPV33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

MMC2107 – Rev. 2.0
MOTOROLA
The software also specifies whether the QADC is to perform a single
pass through the queue or is to scan continuously. When a single-scan
mode is selected, the software selects the queue operating mode and
sets the single-scan enable bit. When a continuous-scan mode is
selected, the queue remains active in the selected queue operating
mode after the QADC completes each queue scan sequence.
During queue execution, the QADC reads each CCW from the active
queue and executes conversions in four stages:
During initial sample, a buffered version of the selected input channel is
connected to the sample capacitor at the input of the sample buffer
amplifier.
During the final sample period, the sample buffer amplifier is bypassed,
and the multiplexer input charges the sample capacitor directly. Each
CCW specifies a final input sample time of 2, 4, 8, or 16 QCLK cycles.
When an analog-to-digital conversion is complete, the result is written to
the corresponding location in the result word table. The QADC continues
to sequentially execute each CCW in the queue until the end of the
queue is detected or a pause bit is found in a CCW.
When the pause bit is set in the current CCW, the QADC stops execution
of the queue until a new trigger event occurs. The pause status flag bit
is set, which may cause an interrupt to notify the software that the queue
has reached the pause state. After the trigger event occurs, the paused
state ends and the QADC continues to execute each CCW in the queue
until another pause is encountered or the end of the queue is detected.
The end-of-queue condition is indicated by:
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Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
Initial sample
Final sample
Resolution
The CCW channel field is programmed with 63 ($3F) to specify the
end of the queue.
The end-of-queue 1 is implied by the beginning of queue 2, which
is specified in the BQ2 field in QACR2.
The physical end of the queue RAM space defines the end of
either queue.
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Queued Analog-to-Digital Converter (QADC)
Technical Data
Digital Control
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