MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 485

• Manufacturer Part Number: MMC2107CFCPV33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCPV33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

18.10.11 Result Word Table
MMC2107 – Rev. 2.0
MOTOROLA
NOTE:
The result word table is a RAM, 64 words long and 10 bits wide. An entry
is written by the QADC after completing an analog conversion specified
by the corresponding CCW table entry. Software can read or write the
result word table, but in normal operation, the software reads the result
word table to obtain analog conversions from the QADC.
Unimplemented bits are read as 0s, and write operations do not have
any effect.
While there is only one result word table, the data can be accessed in
three different data formats:
The left justified, signed format corresponds to a half-scale, offset binary,
two’s complement data format. The data is routed onto the IPbus
according to the selected format. The address used to access the table
determines the data alignment format. All write operations to the result
word table are right justified.
The three result data formats are produced by routing the RAM bits onto
the data bus. The software chooses among the three formats by reading
the result at the memory address which produces the desired data
alignment.
The result word table is read/write accessible by software. During normal
operation, applications software only needs to read the result table.
Write operations to the table may occur during test or debug breakpoint
operation. When locations in the CCW table are not used by an
application, software could use the corresponding locations in the result
word table as scratch pad RAM, remembering that only 10 bits are
implemented. The result alignment is only implemented for software
read operations. Since write operations are not the normal use for the
result registers, only one write data format is supported, which is right
justified data.
Some write operations, like bit manipulation, may not operate as
expected because the hardware cannot access a true 16-bit value.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
Right justified in the 16-bit word, with 0s in the higher order unused
bits
Left justified, with the most significant bit inverted to form a sign bit,
and 0s in the unused lower order bits
Left justified, with 0s in the lower order unused bits
Go to: www.freescale.com
Queued Analog-to-Digital Converter (QADC)
Technical Data
Digital Control
485