MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 519
MMC2107CFCPV33
Manufacturer Part Number
MMC2107CFCPV33
Description
IC MCU 33MHZ 128K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Datasheet
1.MMC2107CFCAF33.pdf
(618 pages)
Specifications of MMC2107CFCPV33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
32
Number Of Timers
4 bit
Operating Supply Voltage
0 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available
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19.10 Bus Monitor
MMC2107 – Rev. 2.0
MOTOROLA
Figure 19-6. Internal (Show) Cycle Followed by External 1-Clock Write
A{22:0], TSIZ[1:0]
CLKOUT
CSE[1:0]
TA, TEA
EB[3:0]
D[31:0]
SHS
R/W
CS
OE
The bus monitor can be set detects excessively long bus access
termination response times. Whenever an undecoded address is
accessed or a peripheral is inoperative, the access is not terminated and
the bus is potentially locked up while it waits for the required response.
The bus monitor monitors the cycle termination response times during a
bus cycle. If the cycle termination response time exceeds a programmed
count, the bus monitor asserts an internal bus error.
The bus monitor monitors the cycle termination response time (in system
clock cycles) by using a programmable maximum allowable response
period. There are four selectable response time periods for the bus
monitor, selectable among 8, 16, 32, and 64 system clock cycles. The
periods are selectable with the BMT[1:0] field in the chip configuration
module CCR. The programmability of the timeout allows for varying
external peripheral response times. The monitor is cleared and restarted
Freescale Semiconductor, Inc.
For More Information On This Product,
External Bus Interface Module (EBI)
INTERNAL CYCLE
Go to: www.freescale.com
A1
SHOW
D1
EXTERNAL WRITE
DATA
A2
00
External Bus Interface Module (EBI)
D2
Technical Data
Bus Monitor
519
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