MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 9

• Manufacturer Part Number: MMC2107CFCPV33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCPV33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

MMC2107 – Rev. 2.0
MOTOROLA
4.5.3
4.5.3.1
4.5.3.2
4.5.3.3
4.5.3.4
4.5.3.5
4.5.3.6
4.5.3.7
4.5.3.8
4.5.3.9
4.5.3.10
4.5.3.11
4.5.4
4.5.4.1
4.5.4.2
4.5.4.3
4.5.5
4.5.5.1
4.5.5.2
4.5.5.3
4.5.5.4
4.5.6
4.5.6.1
4.5.6.2
4.5.7
4.5.8
4.5.8.1
4.5.8.2
4.5.8.3
4.5.8.4
4.5.9
4.5.9.1
4.5.9.2
4.5.9.3
4.5.9.4
4.5.9.5
4.5.9.6
Freescale Semiconductor, Inc.
For More Information On This Product,
External Memory Interface Signals . . . . . . . . . . . . . . . . . .122
Edge Port Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Serial Peripheral Interface Module Signals . . . . . . . . . . . . 125
Serial Communications Interface Module Signals . . . . . . . 125
Timer Signals (ICOC1[3:0] and ICOC2[3:0]) . . . . . . . . . . . 126
Analog-to-Digital Converter Signals . . . . . . . . . . . . . . . . . . 126
Debug and Emulation Support Signals . . . . . . . . . . . . . . . 127
Data Bus (D[31:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Show Cycle Strobe (SHS) . . . . . . . . . . . . . . . . . . . . . . .123
Emulation Mode Chip Selects (CSE[1:0]) . . . . . . . . . . . 123
Transfer Code (TC[2:0]) . . . . . . . . . . . . . . . . . . . . . . . . . 123
Read/Write (R/W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Address Bus (A[22:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Chip Select (CS[3:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Output Enable (OE) . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
External Interrupts (INT[7:6]) . . . . . . . . . . . . . . . . . . . . . 124
External Interrupts (INT[5:2]) . . . . . . . . . . . . . . . . . . . . . 124
External Interrupts (INT[1:0]) . . . . . . . . . . . . . . . . . . . . . 125
Master Out/Slave In (MOSI). . . . . . . . . . . . . . . . . . . . . . 125
Master In/Slave Out (MISO). . . . . . . . . . . . . . . . . . . . . . 125
Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Slave Select (SS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Receive Data (RXD1 and RXD2) . . . . . . . . . . . . . . . . . . 125
Transmit Data (TXD1 and TXD2). . . . . . . . . . . . . . . . . . 126
Analog Inputs (PQA[4:3], PQA[1:0],
Analog Reference (V
Test Reset (TRST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Test Clock (TCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Test Mode Select (TMS) . . . . . . . . . . . . . . . . . . . . . . . . 127
Test Data Input (TDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Test Data Output (TDO). . . . . . . . . . . . . . . . . . . . . . . . . 127
Transfer Acknowledge (TA) . . . . . . . . . . . . . . . . . . . . . . 123
Transfer Error Acknowledge (TEA) . . . . . . . . . . . . . . . . 123
Enable Byte (EB[3:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Analog Supply (V
Positive Supply (V
Debug Event (DE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
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and PQB[3:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table of Contents
DDA
DDH
RH
and V
) . . . . . . . . . . . . . . . . . . . . . . . . . 126
and V
SSA
RL
) . . . . . . . . . . . . . . . . . .126
) . . . . . . . . . . . . . . . . . 126
Table of Contents
Technical Data
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