MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 98

• Manufacturer Part Number: MMC2107CFCPV33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCPV33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Chip Configuration Module (CCM)
Technical Data
98
RPLLSEL — PLL Mode Select Bit
RPLLREF — PLL Reference Bit
RLOAD — Pad Driver Load Bit
BOOTPS — Boot Port Size Bit
BOOTSEL — Boot Select Bit
When the PLL is enabled, the read-only RPLLSEL bit reflects the
default PLL mode.
The default PLL mode can be overridden during reset configuration.
If the default mode is overridden, the PLLSEL bit in the clock module
SYNSR reflects the PLL mode.
When the PLL is enabled in normal PLL mode, the read-only
RPLLREF bit reflects the default PLL reference.
The default PLL reference can be overridden during reset
configuration. If the default mode is overridden, the PLLREF bit in the
clock module SYNSR reflects the PLL reference.
The read-only RLOAD bit reflects the pad driver strength
configuration.
The default function of the pad driver strength can be overridden
during reset configuration. If the default mode is overridden, the
LOAD bit in CCR reflects the pad driver strength configuration.
If the boot device is configured to be external, the read-only BOOTPS
bit reflects the default selection for the boot port size.
The default function of the boot port size can be overridden during
reset configuration. If the default mode is overridden, the PS bit in
CSCR0 reflects the boot device port size configuration.
This read-only bit reflects the default selection for the boot device.
Freescale Semiconductor, Inc.
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1 = Normal PLL mode
0 = 1:1 PLL mode
1 = Crystal oscillator is PLL reference.
0 = External clock is PLL reference.
1 = Full drive strength
0 = Default drive strength
1 = Boot device uses 32-bit port.
0 = Boot device uses 16-bit port.
1 = Boot from external boot device
0 = Boot from internal boot device
Chip Configuration Module (CCM)
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MMC2107 – Rev. 2.0
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