MC68HC711D3CFN2 Freescale Semiconductor, MC68HC711D3CFN2 Datasheet - Page 19

• Manufacturer Part Number: MC68HC711D3CFN2
• Description: IC MCU 2MHZ 4K OTP 44-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711D3CFN2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 26
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

2.10.1 Port A
2.10.2 Port B
2.10.3 Port C
TECHNICAL DATA
Port A can be read at any time. Inputs return the pin level; outputs return the pin driver
input level. If written, port A stores the data in an internal latch. It drives the pins only
if they are configured as outputs. Writes to port A do not change the pin state when
the pins are configured for timer output compares.
Out of reset, port A bits 7 and [3:0] are general high impedance inputs, while bits [6:4]
are outputs, driving low. Bidirectional lines PA7 and PA3 in PACTL are not changed
and do not have any effect on those bits. When the output compare functions associ-
ated with these pins are disabled, the DDR bits in PACTL govern the I/O state.
Refer to SECTION 6 PARALLEL I/O.
Port B is an 8-bit general-purpose I/O port with a data register (PORTB) and a data
direction register (DDRB). In single-chip mode, port B pins are general-purpose I/O
pins (PB[7:0]). In the expanded multiplexed mode, all of the port B pins act as the high-
order address bits (ADDR[15:8]) of the address bus.
Port B can be read at any time. Inputs return the sensed levels at the pin, while outputs
return the input level of the port B pin drivers. If port B is written, the data is stored in
an internal latch and can be driven only if port B is configured as general-purpose out-
puts in single-chip or bootstrap modes.
Port B pins are general-purpose inputs out of reset in single-chip and bootstrap
modes. These pins are outputs (the high order address bits) out of reset in expanded
multiplexed and test modes.
Refer to SECTION 6 PARALLEL I/O.
Port C is an 8-bit general-purpose I/O port with a data register (PORTC) and a data
direction register (DDRC). In the single-chip mode, port C pins are general-purpose I/
O pins (PC[7:0]). In the expanded multiplexed mode, port C pins are configured as
multiplexed address/data pins. During the address cycle, bits [7:0] of the address are
output on PC[7:0]. During the data cycle, bits [7:0] (PC[7:0]) are bidirectional data pins
controlled by the R/W signal.
Port C can be read at any time. Inputs return the sensed levels at the pin, while outputs
return the input level of the port C pin drivers. If port C is written, the data is stored in
an internal latch and can be driven only if port C is configured for general-purpose out-
puts in single-chip or bootstrap mode. Port C pins are general-purpose inputs out of
reset in single-chip and bootstrap modes. These pins are multiplexed low-order ad-
dress and data bus lines out of reset in expanded multiplexed and test modes.
The CWOM control bit in the PIOC register disables port C's P-channel output driver.
CWOM simultaneously affects all eight bits of port C. Because the N-channel driver is
not affected by CWOM, setting CWOM causes port C to become an open-drain-type
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PIN DESCRIPTIONS
2-7