MC68HC711D3CFN2 Freescale Semiconductor, MC68HC711D3CFN2 Datasheet - Page 41

• Manufacturer Part Number: MC68HC711D3CFN2
• Description: IC MCU 2MHZ 4K OTP 44-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711D3CFN2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 26
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

HPRIO — Highest Priority I-Bit Interrupt and Miscellaneous
RBOOT — Read Bootstrap ROM
SMOD — Special Mode Select
MDA — Mode Select A
IRVNE — Internal Read Visibility/Not E
TECHNICAL DATA
RESET:
The values of the RBOOT, SMOD, IRVNE, and MDA at reset depend on the mode dur-
ing initialization. Refer to Table 4-2.
Has meaning only when the SMOD bit is a one (special bootstrap mode or special test
mode). At all other times this bit is clear and cannot be written.
This bit reflects the inverse of the MODB input pin at the rising edge of reset. It is set
if the MODB input pin is low during reset. If MODB is high during reset, it is cleared.
SMOD can be cleared under software control from the special modes, thus changing
the operating mode of the MCU. SMOD can never be set by software.
The mode select A bit reflects the status of the MODA input pin at the rising edge of
reset. While the SMOD bit is set (special bootstrap or special test mode in effect), the
MDA bit can be written, thus changing the operating mode of the MCU. When the
SMOD bit is clear, the MODA bit is read-only and the operating mode cannot be
changed without going through a reset sequence.
The IRVNE control bit allows internal read accesses to be available on the external
data bus during factory testing or emulation. If this capability is used for other purpos-
es, bus conflicts can occur because the bidirectional data bus is driven out during a
read of internal addresses, even though the R/W line suggests a high impedance
read mode.
In single-chip modes, this bit determines whether the E clock drives out of the chip.
0 = Bootloader ROM disabled and not in map
1 = Bootloader ROM enabled and located in map at $BF40–$BFFF
0 = Normal mode variation in effect
1 = Special mode variation in effect
0 = Normal single-chip or special bootstrap mode in effect
1 = Normal expanded or special test mode in effect
0 = No internal read visibility on external bus
1 = Internal read data driven out data bus
0 = E driven out
1 = E pin driven low
RBOOT
Bit 7
—
SMOD
—
Freescale Semiconductor, Inc.
6
OPERATING MODES AND ON-CHIP MEMORY
For More Information On This Product,
MDA
Go to: www.freescale.com
—
5
IRVNE
—
4
PSEL3
3
0
PSEL2
2
1
PSEL1
1
0
$003C
PSEL0
Bit 0
1
4-7