MC68HC16Z1CFC16 Freescale Semiconductor, MC68HC16Z1CFC16 Datasheet - Page 104

• Manufacturer Part Number: MC68HC16Z1CFC16
• Description: IC MPU 1K RAM 16MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CFC16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

4.14.4.6 BDM Serial Interface
4-44
MICROSEQUENCER
The BDM serial interface uses a synchronous protocol similar to that of the Freescale
serial peripheral interface (SPI).
use BDM with a development system.
The development system serves as the master of the serial link, and is responsible for
the generation of the serial interface clock signal (DSCLK).
Serial clock frequency range is from DC to one-half the CPU16 clock frequency. If
DSCLK is derived from the CPU16 system clock, development system serial logic can
be synchronized with the target processor.
The serial interface operates in full-duplex mode. Data transfers occur on the falling
edge of DSCLK and are stable by the following rising edge of DSCLK. Data is trans-
mitted MSB first, and is latched on the rising edge of DSCLK.
The serial data word is 17 bits wide, which includes 16 data bits and a status/control
bit. Bit 16 indicates status of CPU-generated messages.
Command and data transfers initiated by the development system must clear bit 16.
All commands that return a result return 16 bits of data plus one status bit.
SYNCHRONIZE
EXECUTION
STATUS
UNIT
Figure 4-7 BDM Serial I/O Block Diagram
Freescale Semiconductor, Inc.
For More Information On This Product,
RCV DATA LATCH
REGISTER BUS
PARALLEL OUT
INSTRUCTION
PARALLEL IN
SERIAL OUT
SERIAL IN
CPU
CENTRAL PROCESSING UNIT
16
16
CONTROL
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LOGIC
Figure 4-7
is a diagram of the serial logic required to
DSCLK
DSO
DSI
STATUS
0
DEVELOPMENT SYSTEM
COMMAND LATCH
PARALLEL OUT
RESULT LATCH
CONTROL
PARALLEL IN
SERIAL OUT
LOGIC
SERIAL IN
DATA
DATA
16
16
M68HC16 Z SERIES
USER’S MANUAL
SERIAL
CLOCK
COM BLOCK
BDM SER