MC68HC16Z1CFC16 Freescale Semiconductor, MC68HC16Z1CFC16 Datasheet - Page 131

• Manufacturer Part Number: MC68HC16Z1CFC16
• Description: IC MPU 1K RAM 16MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CFC16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

5.4.3 Halt Monitor
5.4.4 Spurious Interrupt Monitor
5.4.5 Software Watchdog
M68HC16 Z SERIES
USER’S MANUAL
The monitor does not check DSACK response on the external bus unless the CPU16
initiates a bus cycle. The BME bit in SYPCR enables the internal bus monitor for inter-
nal to external bus cycles. If a system contains external bus masters, an external bus
monitor must be implemented and the internal-to-external bus monitor option must be
disabled.
When monitoring transfers to an 8-bit port, the bus monitor does not reset until both
byte accesses of a word transfer are completed. Monitor time-out period must be at
least twice the number of clocks that a single byte access requires.
The halt monitor responds to an assertion of the HALT signal on the internal bus,
caused by a double bus fault. A flag in the reset status register (RSR) can indicate that
the last reset was caused by the halt monitor. Halt monitor reset can be inhibited by
the halt monitor enable (HME) bit in SYPCR. Refer to
more information.
During interrupt exception processing, the CPU16 normally acknowledges an interrupt
request, arbitrates among various sources of interrupt, recognizes the highest priority
source, and then acquires a vector or responds to a request for autovectoring. The
spurious interrupt monitor asserts the internal bus error signal (BERR) if no interrupt
arbitration occurs during interrupt exception processing. The assertion of BERR caus-
es the CPU16 to load the spurious interrupt exception vector into the program counter.
The spurious interrupt monitor cannot be disabled. Refer to
information. For detailed information about interrupt exception processing, refer to
4.13
The software watchdog is controlled by the software watchdog enable (SWE) bit in
SYPCR. When enabled, the watchdog requires that a service sequence be written to
the software watchdog service register (SWSR) on a periodic basis. If servicing does
not take place, the watchdog times out and asserts the RESET signal.
Each time the service sequence is written, the software watchdog timer restarts. The
sequence to restart the software watchdog consists of the following steps:
• Write $55 to SWSR.
• Write $AA to SWSR.
Exceptions.
Freescale Semiconductor, Inc.
BMT[1:0]
For More Information On This Product,
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01
10
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Table 5-8 Bus Monitor Period
SYSTEM INTEGRATION MODULE
Go to: www.freescale.com
Bus Monitor Time-Out Period
64 system clocks
32 system clocks
16 system clocks
8 system clocks
5.6.5.2 Double Bus Faults
5.8 Interrupts
for further
5-25
for