MC68HC16Z1CFC16 Freescale Semiconductor, MC68HC16Z1CFC16 Datasheet - Page 243

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MC68HC16Z1CFC16

Manufacturer Part Number
MC68HC16Z1CFC16
Description
IC MPU 1K RAM 16MHZ 132-PQFP
Manufacturer
Freescale Semiconductor
Series
HC16r
Datasheets

Specifications of MC68HC16Z1CFC16

Core Processor
CPU16
Core Size
16-Bit
Speed
16MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
132-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-

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10.2.1.2 Privilege Levels
10.2.1.3 MCCI Interrupts
M68HC16 Z SERIES
USER’S MANUAL
To ensure that the MCCI stops in a known state, assert the STOP bit before executing
the CPU LPSTOP instruction. Before asserting the STOP bit, disable the SPI (clear
the SPE bit) and disable the SCI receivers and transmitters (clear the RE and TE bits).
Complete transfers in progress before disabling the SPI and SCI interfaces.
Once the STOP bit is asserted, it can be cleared by system software or by reset.
The supervisor bit (SUPV) in the MMCR has no effect since the CPU16 operates only
in the supervisor mode.
The interrupt request level of each of the three MCCI interfaces can be programmed
to a value of zero (interrupts disabled) through seven (highest priority). These levels
are selected by the ILSCIA and ILSCIB fields in the SCI interrupt level register (ILSCI)
and the ILSPI field in the SPI interrupt level register (ILSPI). In case two or more MCCI
submodules request an interrupt simultaneously and are assigned the same interrupt
request level, the SPI submodule is given the highest priority and SCIB is given the
lowest.
When an interrupt is requested which is at a higher level than the interrupt mask in the
CPU status register, the CPU initiates an interrupt acknowledge cycle. During this cy-
cle, the MCCI compares its interrupt request level to the level recognized by the CPU.
If a match occurs, arbitration with other modules begins.
Interrupting modules present their arbitration number on the IMB, and the module with
the highest number wins. The arbitration number for the MCCI is programmed into the
interrupt arbitration (IARB) field of the MMCR. Each module should be assigned a
unique arbitration number. The reset value of the IARB field is $0, which prevents the
MCCI from arbitrating during an interrupt acknowledge cycle. The IARB field should
be initialized by system software to a value from $F (highest priority) through $1 (low-
est priority). Otherwise, the CPU identifies any interrupts generated as spurious and
takes a spurious-interrupt exception.
If the MCCI wins the arbitration, it generates an interrupt vector that uniquely identifies
the interrupting serial interface. The six MSBs are read from the interrupt vector (INTV)
field in the MCCI interrupt vector register (MIVR). The two LSBs are assigned by the
MCCI according to the interrupting serial interface, as indicated in
MULTICHANNEL COMMUNICATION INTERFACE
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 10-1 MCCI Interrupt Vectors
Go to: www.freescale.com
Interface
SCIA
SCIB
SPI
INTV[1:0]
00
01
10
Table
10-1.
10-3

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