MC68HC16Z1CFC16 Freescale Semiconductor, MC68HC16Z1CFC16 Datasheet - Page 250

• Manufacturer Part Number: MC68HC16Z1CFC16
• Description: IC MPU 1K RAM 16MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CFC16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

SCK (CPOL = 0)
SCK (CPOL = 1)
10.3.4.2 CPHA = 1 Transfer Format
10-10
(FROM MASTER)
(FROM SLAVE)
SS (TO SLAVE)
MISO
Figure 10-4
equals one. Two waveforms are shown for SCK, one for CPOL equal to zero and an-
other for CPOL equal to one. The diagram may be interpreted as a master or slave
timing diagram since the SCK, MISO and MOSI pins are directly connected between
the master and the slave. The MISO signal shown is the output from the slave and the
MOSI signal shown is the output from the master. The SS line is the slave select input
to the slave.
For a master, writing to the SPDR initiates the transfer. For a slave, the first edge of
SCK indicates the start of a transfer. The SPI is left-shifted on the first and each suc-
ceeding odd clock edge, and data is latched on the second and succeeding even clock
edges.
SCK is inactive for the last half of the eighth SCK cycle. For a master, SPIF is set at
the end of the eighth SCK cycle (after the seventeenth SCK edge). Since the last SCK
edge occurs in the middle of the eighth SCK cycle, however, the slave has no way of
knowing when the end of the last SCK cycle occurs. The slave therefore considers the
transfer complete after the last bit of serial data has been sampled, which corresponds
to the middle of the eighth SCK cycle.
When CPHA is one, the SS line may remain at its active low level between transfers.
This format is sometimes preferred in systems having a single fixed master and only
one slave that needs to drive the MISO data line.
MOSI
(FOR REFERENCE)
SCK CYCLE #
* NOT DEFINED BUT NORMALLY LSB OF PREVIOUSLY TRANSMITTED CHARACTER
is a timing diagram of an 8-bit, MSB-first SPI transfer in which CPHA
*
Figure 10-4 CPHA = 1 SPI Transfer Format
MULTICHANNEL COMMUNICATION INTERFACE
Freescale Semiconductor, Inc.
MSB
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M68HC16 Z SERIES
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USER’S MANUAL
LSB
CPHA = 1 SPI TRANSFER