MC68HC16Z1CFC16 Freescale Semiconductor, MC68HC16Z1CFC16 Datasheet - Page 268

• Manufacturer Part Number: MC68HC16Z1CFC16
• Description: IC MPU 1K RAM 16MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CFC16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

11.3.3 Single-Step Mode
11.3.4 Test Mode
11.4 Polled and Interrupt-Driven Operation
11.4.1 Polled Operation
11-4
Two bits in GPTMCR support GPT debugging without using BDM. When the STOPP
bit is asserted, the prescaler and the pulse accumulator stop counting and changes at
input pins are ignored. Reads of the GPT pins return the state of the pin when STOPP
was set. After STOPP is set, the INCP bit can be set to increment the prescaler and
clock the input synchronizers once. The INCP bit is self-negating after the prescaler is
incremented. INCP can be set repeatedly. The INCP bit has no effect when the
STOPP bit is not set.
Test mode is used during Freescale factory testing. The GPT has no dedicated test-
mode control register; all GPT testing is done under control of the system integration
module.
Normal GPT function can be polled or interrupt-driven. All GPT functions have an as-
sociated status flag and an associated interrupt. The timer interrupt flag registers
(TFLG1 and TFLG2) contain status flags used for polled and interrupt-driven opera-
tion. The timer mask registers (TMSK1 and TMSK2) contain interrupt control bits. Con-
trol routines can monitor GPT operation by polling the status registers. When an event
occurs, the control routine transfers control to a service routine that handles that event.
If interrupts are enabled for an event, the GPT requests interrupt service when the
event occurs. Using interrupts does not require continuously polling the status flags to
see if an event has taken place. However, to disable the interrupt request, status flags
must be cleared after an interrupt is serviced.
When an event occurs in the GPT, that event sets a status flag in TFLG1 or TFLG2.
The GPT sets the flags; they cannot be set by the CPU. TFLG1 and TFLG2 are 8-bit
registers that can be accessed individually or as one 16-bit register. The registers are
initialized to zero at reset.
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 11-1
GENERAL-PURPOSE TIMER
Go to: www.freescale.com
shows status flag assignment.
M68HC16 Z SERIES
USER’S MANUAL