MC68HC16Z1CFC16 Freescale Semiconductor, MC68HC16Z1CFC16 Datasheet - Page 279

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MC68HC16Z1CFC16

Manufacturer Part Number
MC68HC16Z1CFC16
Description
IC MPU 1K RAM 16MHZ 132-PQFP
Manufacturer
Freescale Semiconductor
Series
HC16r
Datasheets

Specifications of MC68HC16Z1CFC16

Core Processor
CPU16
Core Size
16-Bit
Speed
16MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
132-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-

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M68HC16 Z SERIES
USER’S MANUAL
PCLK
In event counting mode, the counter increments each time a selected transition of the
pulse accumulator input (PAI) pin is detected. The maximum clocking rate is the sys-
tem clock divided by four.
In gated time accumulation mode a clock increments PACNT while the PAI pin is in
the active state. There are four possible clock sources.
Two bits in the TFLG2 register show pulse accumulator status. The pulse accumulator
flag (PAIF) indicates that a selected edge has been detected at the PAI pin. The pulse
accumulator overflow flag (PAOVF) indicates that the pulse accumulator count has
rolled over from $FF to $00. This can be used to extend the range of the counter be-
yond eight bits.
PAI
CAPTURE/COMPARE CLK
PRESCALER 512
TCNT OVERFLOW
SYNCHRONIZER
DIGITAL FILTER
Figure 11-5 Pulse Accumulator Block Diagram
PACTL
TMSK2
&
Freescale Semiconductor, Inc.
For More Information On This Product,
MUX
DETECT
LOGIC
GENERAL-PURPOSE TIMER
EDGE
Go to: www.freescale.com
MUX
2:1
INTERNAL
DATA BUS
OVERFLOW
ENABLE
TFLG2
8-BIT COUNTER
PACNT
INTERRUPT
REQUESTS
10
11
16/32 PULSE ACC BLOCK
11-15

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