MC68HC16Z1CFC16 Freescale Semiconductor, MC68HC16Z1CFC16 Datasheet - Page 293

• Manufacturer Part Number: MC68HC16Z1CFC16
• Description: IC MPU 1K RAM 16MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CFC16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

M68HC16 Z SERIES
USER’S MANUAL
Num
NOTES:
10. Jitter is the average deviation from the programmed frequency measured over the specified interval at maxi-
1
2
3
4
5
6
1. The base configuration of the MC68HC16Z1, MC68CK16Z1, MC68HC16Z4, and the MC68CK16Z4 requires
2. All internal registers retain data at 0 Hz.
3. Assumes that V
4. Assumes that V
5. Cold start is measured from V
6. Internal VCO frequency (f
7. This parameter is periodically sampled rather than 100% tested.
8. Assumes that a low-leakage external filter network is used to condition clock synthesizer input voltage. Total
9. Proper layout procedures must be followed to achieve specifications.
mum f
nal clock signal. Noise injected into the PLL circuitry via V
frequency increase the J
operation, this parameter should be measured during functional testing of the final system.
a 32.768 kHz crystal reference. The base configuration of the MC68CM16Z1, M68HC16Z2, and the
MC68HC16Z3 requires a 4.194 MHz crystal reference.
oscillator is stable.
is stable, followed by V
vide-by-two circuit that is not in the synthesizer feedback loop.
When X = 0, the divider is enabled, and f
When X = 1, the divider is disabled, and f
X must equal one when operating at maximum specified f
external resistance from the XFC pin due to external leakage must be greater than 15 M to guarantee this
specification. Filter network geometry can vary depending upon operating environment
PLL Reference Frequency Range
System Frequency
PLL Lock Time
VCO Frequency
Limp Mode Clock Frequency
CLKOUT Jitter
MC68HC16Z1
MC68HC16Z2
MC68HC16Z3
On-Chip PLL System Frequency
External Clock Operation
Changing W or Y in SYNCR or exiting from
Warm Start-Up
Cold Start-Up (fast reference option only)
SYNCR X bit = 0
SYNCR X bit = 1
Short term (5 s interval)
Long term (500 s interval)
Slow On-Chip PLL System Frequency
Fast On-Chip PLL System Frequency
LPSTOP
sys
. Measurements are made with the device powered by filtered supplies and clocked by a stable exter-
3
1, 7, 8, 9, 10
DDSYN
1, 7, 8, 9
DDSYN
(V
Characteristic
6
4
DD
Table A-10 25.17-MHz Clock Control Timing
2
and V
and V
DD
is stable, that an external filter is attached to the XFC pin, and that the crystal oscillator
Freescale Semiconductor, Inc.
clk
ramp-up. Lock time is measured from V
For More Information On This Product,
VCO
percentage for a given interval. When jitter is a critical constraint on control system
DD
DDSYN
) is determined by SYNCR W and Y bit values. The SYNCR X bit controls a di-
DDSYN
ELECTRICAL CHARACTERISTICS
are stable, that an external filter is attached to the XFC pin, and that the crystal
1
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= 5.0 Vdc
and V
sys
sys
DD
= f
5
= f
at specified minimum to RESET negated.
VCO
VCO
5%, V
Symbol
4.
2.
f
f
J
f
VCO
f
t
limp
sys
ref
lpll
clk
SS
sys
DDSYN
= 0 Vdc, T
.
DD
and V
4 (f
at specified minimum to RESET negated.
4 (f
–0.05
ref
–1.0
Min
3.2
3.2
20
dc
dc
—
—
—
—
—
—
A
) /128
SS
ref
= T
)
and variation in crystal oscillator
L
to T
2 (f
H
f
sys
f
)
sys
25.17
25.17
25.17
25.17
sys
Max
.
5.2
5.2
1.0
0.5
50
20
50
75
max/2
max
max)
MHz
MHz
MHz
MHz
MHz
Unit
kHz
ms
A-9