MC68HC16Z1CFC16 Freescale Semiconductor, MC68HC16Z1CFC16 Datasheet - Page 377

• Manufacturer Part Number: MC68HC16Z1CFC16
• Description: IC MPU 1K RAM 16MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CFC16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

D.1.1 Condition Code Register
CCR — Condition Code Register
S — STOP Enable
MV — Accumulator M overflow flag
H — Half Carry Flag
EV — Accumulator M Extension Overflow Flag
N — Negative Flag
Z — Zero Flag
V — Overflow Flag
C — Carry Flag
IP[2:0] — Interrupt Priority Field
SM — Saturate Mode Bit
PK[3:0] — Program Counter Address Extension Field
M68HC16 Z SERIES
USER’S MANUAL
15
S
The CCR contains processor status flags, the interrupt priority field, and the program
counter address extension field. The CPU16 has a special set of instructions that ma-
nipulate the CCR.
Set when overflow into AM35 has occurred.
Set when a carry from A3 or B3 occurs during BCD addition.
EV is set when an overflow into AM31 has occurred.
N is set under the following conditions:
Z is set under the following conditions:
Set when two’s complement overflow occurs as the result of an operation.
Set when carry or borrow occurs during arithmetic operation. Also used during shifts
and rotates.
The priority value in this field (0 to 7) is used to mask low priority interrupts.
When SM is set, if either EV or MV is set, data read from AM using TMER or TMET is
given maximum positive or negative value, depending on the state of the AM sign bit
before overflow.
This field is concatenated with the program counter to form a 20-bit address.
0 = Stop CPU16 clocks when LPSTOP instruction is executed.
1 = Perform NOPs when LPSTOP instruction is executed.
• When the MSB is set in the operand of a read operation.
• When the MSB is set in the result of a logic or arithmetic operation.
• When all bits are zero in the operand of a read operation.
• When all bits are zero in the result of a logic or arithmetic operation.
MV
14
13
H
EV
12
Freescale Semiconductor, Inc.
11
N
For More Information On This Product,
10
Z
Go to: www.freescale.com
REGISTER SUMMARY
9
V
C
8
7
IP[2:0]
6
5
SM
4
3
2
PK[3:0]
1
0
D-3