MC68HC16Z1CFC16 Freescale Semiconductor, MC68HC16Z1CFC16 Datasheet - Page 380

• Manufacturer Part Number: MC68HC16Z1CFC16
• Description: IC MPU 1K RAM 16MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CFC16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

SIMCR — SIM Module Configuration Register
D.2.1 SIM Module Configuration Register
EXOFF — External Clock Off
FRZSW — Freeze Software Enable
FRZBM — Freeze Bus Monitor Enable
SHEN[1:0] — Show Cycle Enable
SUPV — Supervisor/User Data Space
D-6
EXOFF FRZSW FRZBM
NOTES:
15
0
RESET:
1. This bit must be left at zero. Pulling DATA11 high during reset ensures this bit remains zero. A one in this bit could
SIMCR controls system configuration. SIMCR can be read or written at any time, ex-
cept for the module mapping (MM) bit, which can only be written once after reset, and
the reserved bit, which is read-only. Write has no effect.
The SHEN field determines how the external bus is driven during internal transfer op-
erations. A show cycle allows internal transfers to be monitored externally.
Table D-3
nal bus arbitration can occur. To prevent bus conflict, external devices must not be se-
lected during show cycles.
This bit has no effect because the CPU16 always operates in the supervisor mode.
allow the MCU to enter an unsupported operating mode.
0 = The CLKOUT pin is driven during normal operation.
1 = The CLKOUT pin is placed in a high-impedance state.
0 = When FREEZE is asserted, the software watchdog and periodic interrupt timer
1 = When FREEZE is asserted, the software watchdog and periodic interrupt timer
0 = When FREEZE is asserted, the bus monitor continues to operate.
1 = When FREEZE is asserted, the bus monitor is disabled.
14
1
continue to operate, allowing interrupts during background debug mode.
are disabled, preventing interrupts during background debug mode.
13
1
indicates whether show cycle data is driven externally, and whether exter-
12
0
0
SHEN[1:0]
DATA11
00
01
10
11
RSVD
Freescale Semiconductor, Inc.
11
For More Information On This Product,
Table D-3 Show Cycle Enable Bits
1
Show cycles disabled, external arbitration enabled
Show cycles enabled, external arbitration disabled
Show cycles enabled, external arbitration enabled
Show cycles enabled, external arbitration enabled;
internal activity is halted by a bus grant
10
0
0
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REGISTER SUMMARY
9
0
SHEN[1:0]
8
0
SUPV
7
1
Action
MM
6
1
5
0
0
4
0
0
3
1
M68HC16 Z SERIES
USER’S MANUAL
2
1
IARB[3:0]
$YFFA00
1
1
0
1