MC68HC16Z1CFC16 Freescale Semiconductor, MC68HC16Z1CFC16 Datasheet - Page 387

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MC68HC16Z1CFC16

Manufacturer Part Number
MC68HC16Z1CFC16
Description
IC MPU 1K RAM 16MHZ 132-PQFP
Manufacturer
Freescale Semiconductor
Series
HC16r
Datasheets

Specifications of MC68HC16Z1CFC16

Core Processor
CPU16
Core Size
16-Bit
Speed
16MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
132-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-

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HME — Halt Monitor Enable
BME — Bus Monitor External Enable
BMT[1:0] — Bus Monitor Timing
D.2.13 Periodic Interrupt Control Register
PICR — Periodic Interrupt Control Register
PIRQL[2:0] — Periodic Interrupt Request Level
M68HC16 Z SERIES
USER’S MANUAL
15
0
0
RESET:
The following equation calculates the time-out period for an externally input clock fre-
quency on both slow and fast reference frequency devices, when f
system clock frequency.
This field selects the bus monitor time-out period. Refer to
PICR sets the interrupt level and vector number for the periodic interrupt timer (PIT).
Bits [10:0] can be read or written at any time. Bits [15:11] are unimplemented and al-
ways read zero.
This field determines the priority of periodic interrupt requests. A value of %000 dis-
ables PIT interrupts.
0 = Halt monitor is disabled.
1 = Halt monitor is enabled.
0 = Disable bus monitor for external bus cycles.
1 = Enable bus monitor for external bus cycles.
14
0
0
Time-out Period
13
0
0
Time-out Period
12
0
0
Table D-7 Bus Monitor Time-Out Period
Freescale Semiconductor, Inc.
11
0
0
For More Information On This Product,
BMT[1:0]
=
00
01
10
11
10
0
------------------------------------------------------------------------------------------------------------------------------- ------------ -
128 Divide Ratio Specified by SWP and SWT[1:0]
=
PIRQL[2:0]
Go to: www.freescale.com
REGISTER SUMMARY
Divide Ratio Specified by SWP and SWT[1:0]
----------------------------------------------------------------------------------------------------------------------- -
9
0
Bus Monitor Time-Out Period
8
0
64 system clocks
32 system clocks
16 system clocks
8 system clocks
7
0
6
0
f
f
sys
ref
5
0
Table
4
0
PIV[7:0]
D-7.
3
1
sys
is equal to the
2
1
$YFFA22
1
1
D-13
0
1

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