MC68HC16Z1CFC16 Freescale Semiconductor, MC68HC16Z1CFC16 Datasheet - Page 395

• Manufacturer Part Number: MC68HC16Z1CFC16
• Description: IC MPU 1K RAM 16MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CFC16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

SPACE[1:0] — Address Space Select
IPL[2:0] — Interrupt Priority Level
AVEC — Autovector Enable
M68HC16 Z SERIES
USER’S MANUAL
Use this option field to select an address space for chip-select assertion or to configure
a chip-select as an interrupt acknowledge strobe for an external device. The CPU16
normally operates in supervisor mode only, but interrupt acknowledge cycles take
place in CPU space.
When SPACE[1:0] is set for CPU space (%00), chip-select logic can be used as an
interrupt acknowledge strobe for an external device. During an interrupt acknowledge
cycle, the interrupt priority level is driven on address lines ADDR[3:1] and is then com-
pared to the value in IPL[2:0]. If the values match, an interrupt acknowledge strobe will
be generated on the particular chip-select pin, provided other option register condi-
tions are met.
This field selects one of two methods of acquiring an interrupt vector during an inter-
rupt acknowledge cycle. This field is not applicable when SPACE[1:0] = %00.
If the chip select is configured to trigger on an interrupt acknowledge cycle
(SPACE[1:0] = %00) and the AVEC field is set to one, the chip-select automatically
generates AVEC and completes the interrupt acknowledge cycle. Otherwise, the vec-
tor must be supplied by the requesting external device to complete the IACK read
cycle.
0 = External interrupt vector enabled
1 = Autovector enabled
Table D-18 Interrupt Priority Level Field Encoding
Table D-18
Table D-17 Address Space Bit Encodings
Freescale Semiconductor, Inc.
Table D-17
For More Information On This Product,
SPACE[1:0]
NOTES:
1. Any level means that chip-select is assert-
IPL[2:0]
shows IPL[2:0] field encoding.
00
01
10
11
ed regardless of the level of the interrupt
acknowledge cycle.
000
001
010
011
100
101
110
111
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REGISTER SUMMARY
shows address space bit encodings.
Interrupt Priority Level
Supervisor/User Space
Supervisor Space
Address Space
Any Level
CPU Space
User Space
1
2
3
4
5
6
7
1
D-21