MC68HC16Z1CFC16 Freescale Semiconductor, MC68HC16Z1CFC16 Datasheet - Page 49

• Manufacturer Part Number: MC68HC16Z1CFC16
• Description: IC MPU 1K RAM 16MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CFC16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

M68HC16 Z SERIES
USER’S MANUAL
EXTAL, XTAL
DSACK[1:0]
ADDR[19:0]
DATA[15:0]
Mnemonic
DSI, DSO,
PADA[7:0]
IPIPE[1:0]
CSBOOT
MODCLK
CLKOUT
CS[10:0]
FREEZE
PCS[3:0]
IRQ[7:1]
BGACK
AN[7:0]
DSCLK
PC[6:0]
FC[2:0]
PE[7:0]
MISO
MOSI
BERR
AVEC
BKPT
HALT
MISO
MOSI
PCLK
PAI
BG
AS
BR
DS
1
1
Address Bus
ADC Analog Input
Address Strobe
Autovector
Bus Error
Bus Grant
Bus Grant
Acknowledge
Breakpoint
Bus Request
System Clockout
Chip-Selects
Boot Chip Select
Data Bus
Data Strobe
Data and Size
Acknowledge
Development Serial In,
Out, Clock
Crystal Oscillator
Function Codes
Freeze
Halt
Interrupt Request Level
Instruction Pipeline
Master In Slave Out
Master In Slave Out
Clock Mode Select
Master Out Slave In
Master Out Slave In
Port ADA
Pulse Accumulator Input
Auxiliary Timer Clock
Port C
Peripheral Chip Select
Port E
Table 3-5 M68HC16 Z-Series Signal Function
Signal Name
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
20-bit address bus used by CPU16
Inputs to ADC multiplexer
Indicates that a valid address is on the address bus
Requests an automatic vector during interrupt acknowledge
Indicates that a bus error has occurred
Indicates that the MCU has relinquished the bus
Indicates that an external device has assumed bus mastership
Signals a hardware breakpoint to the CPU
Indicates that an external device requires bus mastership
System clock output
Select external devices at programmed addresses
Chip select for external boot start-up ROM
16-bit data bus
During a read cycle, indicates that an external device should
place valid data on the data bus. During a write cycle, indicates
that valid data is on the data bus.
Provide asynchronous data transfers and dynamic bus sizing
Serial I/O and clock for background debug mode
Connections for clock synthesizer circuit reference a crystal or
an external oscillator can be used
Identify processor state and current address space
Indicates that the CPU has entered background mode
Suspend external bus activity
Provides an interrupt priority level to the CPU
Indicate instruction pipeline activity
Serial input to QSPI in master mode; serial output from QSPI in
slave mode
Serial input to SPI in master mode; serial output from SPI in
slave mode
Selects the source and type of system clock
Serial output from QSPI in master mode; serial input to QSPI in
slave mode
Serial output from SPI in master mode; serial input to SPI in
slave mode
ADC digital input port signals
Input to the GPT pulse accumulator
GPT external clock input
Port C digital output port signals
QSPI peripheral chip-selects
Port E digital I/O port signals
OVERVIEW
Function
3-15