MC68HC711E20CFN2 Freescale Semiconductor, MC68HC711E20CFN2 Datasheet - Page 109

• Manufacturer Part Number: MC68HC711E20CFN2
• Description: IC MCU 20K 2MHZ OTP 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711E20CFN2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Size: 20KB (20K x 8)
• Program Memory Type: OTP
• Eeprom Size: 512 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

5.3.1 Power-On Reset (POR)
5.3.2 External Reset (RESET)
M68HC11E Family — Rev. 3.2
MOTOROLA
CAUTION:
NOTE:
A positive transition on V
used only for power-up conditions. POR cannot be used to detect drops
in power supply voltages. A 4064 t
the oscillator becomes active allows the clock generator to stabilize. If
RESET is at logical 0 at the end of 4064 t
reset condition until RESET goes to logical 1.
The POR circuit only initializes internal circuitry during cold starts. Refer
to
It is important to protect the MCU during power transitions. Most
M68HC11 systems need an external circuit that holds the RESET pin
low whenever V
voltage level detector, or other external reset circuits, are the usual
source of reset in a system.
The CPU distinguishes between internal and external reset conditions
by sensing whether the reset pin rises to a logic 1 in less than two
E-clock cycles after an internal device releases reset. When a reset
condition is sensed, the RESET pin is driven low by an internal device
for four E-clock cycles, then released. Two E-clock cycles later it is
sampled. If the pin is still held low, the CPU assumes that an external
reset has occurred. If the pin is high, it indicates that the reset was
initiated internally by either the COP system or the clock monitor.
Do not connect an external resistor capacitor (RC) power-up delay
circuit to the reset pin of M68HC11 devices because the circuit charge
time constant can cause the device to misinterpret the type of reset that
occurred.
Figure 2-6. External Reset
Resets and Interrupts
DD
is below the minimum operating level. This external
DD
generates a power-on reset (POR), which is
Circuit.
cyc
(internal clock cycle) delay after
cyc
, the CPU remains in the
Resets and Interrupts
Technical Data
Resets
109