MC68HC711E20CFN2 Freescale Semiconductor, MC68HC711E20CFN2 Datasheet - Page 131

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MC68HC711E20CFN2

Manufacturer Part Number
MC68HC711E20CFN2
Description
IC MCU 20K 2MHZ OTP 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC711E20CFN2

Core Processor
HC11
Core Size
8-Bit
Speed
2MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Size
20KB (20K x 8)
Program Memory Type
OTP
Eeprom Size
512 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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M68HC11E Family — Rev. 3.2
MOTOROLA
Because all clocks are stopped in this mode, all internal peripheral
functions also stop. The data in the internal RAM is retained as long as
V
are unchanged by stop. Therefore, when an interrupt comes to restart
the system, the MCU resumes processing as if there were no
interruption. If reset is used to restart the system, a normal reset
sequence results in which all I/O pins and functions are also restored to
their initial states.
To use the IRQ pin as a means of recovering from stop, the I bit in the
CCR must be clear (IRQ not masked). The XIRQ pin can be used to
wake up the MCU from stop regardless of the state of the X bit in the
CCR, although the recovery sequence depends on the state of the X bit.
If X is set to 0 (XIRQ not masked), the MCU starts up, beginning with the
stacking sequence leading to normal service of the XIRQ request. If X is
set to 1 (XIRQ masked or inhibited), then processing continues with the
instruction that immediately follows the STOP instruction, and no XIRQ
interrupt service is requested or pending.
Because the oscillator is stopped in stop mode, a restart delay may be
imposed to allow oscillator stabilization upon leaving stop. If the internal
oscillator is being used, this delay is required; however, if a stable
external oscillator is being used, the DLY control bit can be used to
bypass this startup delay. The DLY control bit is set by reset and can be
optionally cleared during initialization. If the DLY equal to 0 option is
used to avoid startup delay on recovery from stop, then reset should not
be used as the means of recovering from stop, as this causes DLY to be
set again by reset, imposing the restart delay. This same delay also
applies to power-on reset, regardless of the state of the DLY control bit,
but does not apply to a reset while the clocks are running.
DD
power is maintained. The CPU state and I/O pin levels are static and
Resets and Interrupts
Low-Power Operation
Resets and Interrupts
Technical Data
131

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