MC68HC711E20CFN2 Freescale Semiconductor, MC68HC711E20CFN2 Datasheet - Page 159

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MC68HC711E20CFN2

Manufacturer Part Number
MC68HC711E20CFN2
Description
IC MCU 20K 2MHZ OTP 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC711E20CFN2

Core Processor
HC11
Core Size
8-Bit
Speed
2MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Size
20KB (20K x 8)
Program Memory Type
OTP
Eeprom Size
512 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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M68HC11E Family — Rev. 3.2
MOTOROLA
RCKB — SCI Baud Rate Clock Check Bit (Test)
SCR[2:0] — SCI Baud Rate Select Bits
Selects receiver and transmitter bit rate based on output from baud
rate prescaler stage. Refer to
The prescaler bits, SCP[2:0], determine the highest baud rate, and
the SCR[2:0] bits select an additional binary submultiple ( 1, 2, 4,
through 128) of this highest baud rate. The result of these two
dividers in series is the 16X receiver baud rate clock. The SCR[2:0]
bits are not affected by reset and can be changed at any time,
although they should not be changed when any SCI transfer is in
progress.
Figure 7-8
The prescaler select bits determine the highest baud rate. The rate
select bits determine additional divide by two stages to arrive at the
receiver timing (RT) clock rate. The baud rate clock is the result of
dividing the RT clock by 16.
Serial Communications Interface (SCI)
and
Figure 7-9
illustrate the SCI baud rate timing chain.
Figure 7-8
Serial Communications Interface (SCI)
and
Figure
7-9.
Technical Data
SCI Registers
159

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