MC68HC711E20CFN2 Freescale Semiconductor, MC68HC711E20CFN2 Datasheet - Page 195

• Manufacturer Part Number: MC68HC711E20CFN2
• Description: IC MCU 20K 2MHZ OTP 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711E20CFN2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Size: 20KB (20K x 8)
• Program Memory Type: OTP
• Eeprom Size: 512 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

9.5.7 Timer Interrupt Mask 1 Register
M68HC11E Family — Rev. 3.2
MOTOROLA
NOTE:
Address:
Use this 8-bit register to enable or inhibit the timer input capture and
output compare interrupts.
OC1I–OC4I — Output Compare x Interrupt Enable Bits
I4/O5I — Input Capture 4/Output Compare 5 Interrupt Enable Bit
IC1I–IC3I — Input Capture x Interrupt Enable Bits
Bits in TMSK1 correspond bit for bit with flag bits in TFLG1. Bits in
TMSK1 enable the corresponding interrupt sources.
Reset:
Read:
Write:
If the OCxI enable bit is set when the OCxF flag bit is set, a hardware
interrupt sequence is requested.
When I4/O5 in PACTL is 1, I4/O5I is the input capture 4 interrupt
enable bit. When I4/O5 in PACTL is 0, I4/O5I is the output compare 5
interrupt enable bit.
If the ICxI enable bit is set when the ICxF flag bit is set, a hardware
interrupt sequence is requested.
Figure 9-17. Timer Interrupt Mask 1 Register (TMSK1)
$1022
OC1I
Bit 7
0
OC2I
Timing System
6
0
OC3I
5
0
OC4I
4
0
I4/O5I
3
0
IC1I
2
0
Output Compare
IC2I
1
0
Timing System
Technical Data
Bit 0
IC3I
0
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