MC68HC711E20CFN2 Freescale Semiconductor, MC68HC711E20CFN2 Datasheet - Page 20

• Manufacturer Part Number: MC68HC711E20CFN2
• Description: IC MCU 20K 2MHZ OTP 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711E20CFN2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Size: 20KB (20K x 8)
• Program Memory Type: OTP
• Eeprom Size: 512 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

List of Figures
Technical Data
20
Figure
9-25
9-26
9-27
9-28
10-1
10-2
10-3
10-4
10-5
10-6
11-1
11-2
11-3
11-4
11-5
11-6
11-7
11-8
11-9
11-10 Simple Output Strobe Timing Diagram. . . . . . . . . . . . . . . . . 238
11-11 Port C Input Handshake Timing Diagram. . . . . . . . . . . . . . . 238
11-12 Port C Output Handshake Timing Diagram . . . . . . . . . . . . . 238
11-13 3-State Variation of Output Handshake Timing Diagram
11-14 Multiplexed Expansion Bus Timing Diagram . . . . . . . . . . . . 245
11-15 SPI Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
B-1
Pulse Accumulator Control Register (PACTL) . . . . . . . . . . . 205
A/D Converter Block Diagram . . . . . . . . . . . . . . . . . . . . . . .211
Electrical Model of an A/D Input Pin (Sample Mode) . . . . . . 211
A/D Conversion Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 213
System Configuration Options Register (OPTION) . . . . . . . 214
A/D Control/Status Register (ADCTL) . . . . . . . . . . . . . . . . . 218
Analog-to-Digital Converter
Test Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Timer Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230
POR External Reset Timing Diagram. . . . . . . . . . . . . . . . . . 231
STOP Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . 232
WAIT Recovery from Interrupt Timing Diagram . . . . . . . . . . 233
Interrupt Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Port Read Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Port Write Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Simple Input Strobe Timing Diagram . . . . . . . . . . . . . . . . . .237
Pulse Accumulator Count Register (PACNT) . . . . . . . . . . . . 206
Timer Interrupt Mask 2 Register (TMSK2) . . . . . . . . . . . . . . 207
Timer Interrupt Flag 2 Register (TFLG2) . . . . . . . . . . . . . . . 207
EVBU Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Result Registers (ADR1–ADR4) . . . . . . . . . . . . . . . . . . . 220
(STRA Enables Output Buffer) . . . . . . . . . . . . . . . . . . . . 239
List of Figures
Title
M68HC11E Family — Rev. 3.2
MOTOROLA
Page