MC68HC711E20CFN2 Freescale Semiconductor, MC68HC711E20CFN2 Datasheet - Page 205

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MC68HC711E20CFN2

Manufacturer Part Number
MC68HC711E20CFN2
Description
IC MCU 20K 2MHZ OTP 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC711E20CFN2

Core Processor
HC11
Core Size
8-Bit
Speed
2MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Size
20KB (20K x 8)
Program Memory Type
OTP
Eeprom Size
512 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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9.8.1 Pulse Accumulator Control Register
M68HC11E Family — Rev. 3.2
MOTOROLA
Address:
Four of this register’s bits control an 8-bit pulse accumulator system.
Another bit enables either the OC5 function or the IC4 function, while two
other bits select the rate for the real-time interrupt system.
DDRA7 — Data Direction for Port A Bit 7
PAEN — Pulse Accumulator System Enable Bit
PAMOD — Pulse Accumulator Mode Bit
PEDGE — Pulse Accumulator Edge Control Bit
Reset:
Read:
Write:
Refer to
This bit has different meanings depending on the state of the PAMOD
bit, as shown in
Figure 9-25. Pulse Accumulator Control Register (PACTL)
0 = Pulse accumulator disabled
1 = Pulse accumulator enabled
0 = Event counter
1 = Gated time accumulation
DDRA7
$1026
Bit 7
PAMOD
0
Section 6. Parallel Input/Output (I/O)
0
0
1
1
Table 9-7. Pulse Accumulator Edge Control
PAEN
Timing System
6
0
Table
PEDGE
0
1
0
1
PAMOD
9-7.
5
0
PAI falling edge increments the counter.
PAI rising edge increments the counter.
A 0 on PAI inhibits counting.
A 1 on PAI inhibits counting.
PEDGE
4
0
Action on Clock
DDRA3
3
0
I4/O5
2
0
Ports.
Pulse Accumulator
RTR1
1
0
Timing System
Technical Data
RTR0
Bit 0
0
205

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