MC68HC711E20CFN2 Freescale Semiconductor, MC68HC711E20CFN2 Datasheet - Page 207

• Manufacturer Part Number: MC68HC711E20CFN2
• Description: IC MCU 20K 2MHZ OTP 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711E20CFN2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Size: 20KB (20K x 8)
• Program Memory Type: OTP
• Eeprom Size: 512 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

9.8.3 Pulse Accumulator Status and Interrupt Bits
M68HC11E Family — Rev. 3.2
MOTOROLA
Address:
Address:
The pulse accumulator control bits, PAOVI and PAII, PAOVF and PAIF,
are located within timer registers TMSK2 and TFLG2.
PAOVI and PAOVF — Pulse Accumulator Interrupt Enable
Reset:
Reset:
Read:
Read:
Write:
Write:
The PAOVF status bit is set each time the pulse accumulator count
rolls over from $FF to $00. To clear this status bit, write a 1 in the
corresponding data bit position (bit 5) of the TFLG2 register. The
PAOVI control bit allows configuring the pulse accumulator overflow
for polled or interrupt-driven operation and does not affect the state of
PAOVF. When PAOVI is 0, pulse accumulator overflow interrupts are
inhibited, and the system operates in a polled mode, which requires
that PAOVF be polled by user software to determine when an
overflow has occurred. When the PAOVI control bit is set, a hardware
Figure 9-27. Timer Interrupt Mask 2 Register (TMSK2)
Figure 9-28. Timer Interrupt Flag 2 Register (TFLG2)
$1024
$1025
Bit 7
Bit 7
TOF
TOI
0
0
= Unimplemented
= Unimplemented
RTIF
RTII
Timing System
6
0
6
0
PAOVF
PAOVI
and Overflow Flag
5
0
5
0
PAIF
PAII
4
0
4
0
3
0
3
0
2
0
2
0
Pulse Accumulator
PR1
1
0
1
0
Timing System
Technical Data
Bit 0
Bit 0
PR0
0
0
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