MC68HC711E20CFN2 Freescale Semiconductor, MC68HC711E20CFN2 Datasheet - Page 208

• Manufacturer Part Number: MC68HC711E20CFN2
• Description: IC MCU 20K 2MHZ OTP 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711E20CFN2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Size: 20KB (20K x 8)
• Program Memory Type: OTP
• Eeprom Size: 512 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Timing System
Technical Data
208
PAII and PAIF — Pulse Accumulator Input Edge Interrupt Enable Bit
interrupt request is generated each time PAOVF is set. Before leaving
the interrupt service routine, software must clear PAOVF by writing to
the TFLG2 register.
The PAIF status bit is automatically set each time a selected edge is
detected at the PA7/PAI/OC1 pin. To clear this status bit, write to the
TFLG2 register with a 1 in the corresponding data bit position (bit 4).
The PAII control bit allows configuring the pulse accumulator input
edge detect for polled or interrupt-driven operation but does not affect
setting or clearing the PAIF bit. When PAII is 0, pulse accumulator
input interrupts are inhibited, and the system operates in a polled
mode. In this mode, the PAIF bit must be polled by user software to
determine when an edge has occurred. When the PAII control bit is
set, a hardware interrupt request is generated each time PAIF is set.
Before leaving the interrupt service routine, software must clear PAIF
by writing to the TFLG2 register.
Timing System
and Flag
M68HC11E Family — Rev. 3.2
MOTOROLA