MC68HC711E20CFN2 Freescale Semiconductor, MC68HC711E20CFN2 Datasheet - Page 21

• Manufacturer Part Number: MC68HC711E20CFN2
• Description: IC MCU 20K 2MHZ OTP 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711E20CFN2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Size: 20KB (20K x 8)
• Program Memory Type: OTP
• Eeprom Size: 512 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

M68HC11E Family — Rev. 3.2
MOTOROLA
Technical Data — M68HC11E Family
Table
2-1
3-1
3-2
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
5-1
5-2
5-3
5-4
5-5
6-1
6-2
7-1
8-1
9-1
9-2
Port Signal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Reset Vector Comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Hardware Mode Select Summary. . . . . . . . . . . . . . . . . . . . . . . 82
Write Access Limited Registers . . . . . . . . . . . . . . . . . . . . . . . .85
EEPROM Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
RAM Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
EEPROM Block Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
EEPROM Block Protect in MC68HC811E2 MCUs . . . . . . . . .100
EEPROM Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
COP Timer Rate Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Reset Cause, Reset Vector, and Operating Mode . . . . . . . . .114
Highest Priority Interrupt Selection . . . . . . . . . . . . . . . . . . . . . 120
Interrupt and Reset Vector Assignments . . . . . . . . . . . . . . . . 121
Stacking Order on Entry to Interrupts . . . . . . . . . . . . . . . . . . .122
Input/Output Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Parallel I/O Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
Baud Rate Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
SPI Clock Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Timer Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Timer Control Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 183
List of Tables
Title
List of Tables
Technical Data
Page
21