MC68HC711E20CFN2 Freescale Semiconductor, MC68HC711E20CFN2 Datasheet - Page 215

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MC68HC711E20CFN2

Manufacturer Part Number
MC68HC711E20CFN2
Description
IC MCU 20K 2MHZ OTP 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC711E20CFN2

Core Processor
HC11
Core Size
8-Bit
Speed
2MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Size
20KB (20K x 8)
Program Memory Type
OTP
Eeprom Size
512 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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10.5 Conversion Process
M68HC11E Family — Rev. 3.2
MOTOROLA
DLY — Enable Oscillator Startup Delay Bit
CME — Clock Monitor Enable Bit
Bit 2 — Not implemented
CR[1:0] — COP Timer Rate Select Bits
The A/D conversion sequence begins one E-clock cycle after a write to
the A/D control/status register, ADCTL. The bits in ADCTL select the
channel and the mode of conversion.
An input voltage equal to V
to V
ratiometric conversions of this type, the source of each analog input
should use V
Refer to
Always reads 0
Refer to
System.
RH
0 = The oscillator startup delay coming out of stop is bypassed and
1 = A delay of approximately 4000 E-clock cycles is imposed as the
converts to $FF (full scale), with no overflow indication. For
the MCU resumes processing within about four bus cycles.
MCU is started up from the stop power-saving mode. This
delay allows the crystal oscillator to stabilize.
Analog-to-Digital (A/D) Converter
Section 5. Resets and
Section 5. Resets and Interrupts
RH
as the supply voltage and be referenced to V
RL
converts to $00 and an input voltage equal
Interrupts.
Analog-to-Digital (A/D) Converter
and
Section 9. Timing
Conversion Process
Technical Data
RL
.
215

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