MC68HC711E20CFN2 Freescale Semiconductor, MC68HC711E20CFN2 Datasheet - Page 285

• Manufacturer Part Number: MC68HC711E20CFN2
• Description: IC MCU 20K 2MHZ OTP 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711E20CFN2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Size: 20KB (20K x 8)
• Program Memory Type: OTP
• Eeprom Size: 512 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Main Bootloader Program
AN1060 — Rev. 1.0
MOTOROLA
Samples taken at [7] detect the failing edge of the start bit and verify it is
a logic 0. Samples taken at the middle of what the receiver interprets as
the first five bit times [8] detect logic 0s. The sample taken at the middle
of what the receiver interprets as bit 5 [9] may detect either a 0 or a 1
because the receive data has a rising transition at about this time. The
samples for bits 6 and 7 detect 1s, causing the receiver to think the
received character was $C0 or $E0 [10] at 7812 baud instead of the $FF
which was sent at 1200 baud. The stop bit sample detects a 1 as
expected [11], but this detection is actually in the middle of bit 0 of the
1200 baud $FF character. The SCI receiver is not confused by the rest
of the 1200 baud $FF character because the receive data line is high
[12] just as it would be for the idle condition. If a character other than $FF
is sent as the first character, an SCI receive error could result.
Figure 3
MC68HC711E9. This bootloader demonstrates the most important
features of the bootloaders used on all M68HC11 Family members. For
complete listings of other M68HC11 versions, refer to
MC68HC711E9 Bootloader ROM
and to Appendix B of the M68HC11 Reference Manual, Motorola
document order number M68HC11RM/AD.
The reset vector in the boot ROM points to the start [1] of this program.
The initialization block [2] establishes starting conditions and sets up the
SCI and port D. The stack pointer is set because there are push and pull
instructions in the bootloader program. The X index register is pointed at
the start of the register block ($1000) so indexed addressing can be
used. Indexed addressing takes one less byte of ROM space than
extended instructions, and bit manipulation instructions are not available
in extended addressing forms. The port D wire-OR mode (DWOM) bit in
the serial peripheral interface control register (SPCR) is set to configure
port D for wired-OR operation to minimize potential conflicts with
external systems that use the PD1/TxD pin as an input. The baud rate
for the SCI is initially set to 7812 baud at a 2-MHz E-clock rate but can
automatically switch to 1200 baud based on the first character received.
is a flowchart of the main bootloader program in the
at the end of this application note,
Listing 3.
Application Note
285