MC68HC711E20CFN2 Freescale Semiconductor, MC68HC711E20CFN2 Datasheet - Page 42

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MC68HC711E20CFN2

Manufacturer Part Number
MC68HC711E20CFN2
Description
IC MCU 20K 2MHZ OTP 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC711E20CFN2

Core Processor
HC11
Core Size
8-Bit
Speed
2MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Size
20KB (20K x 8)
Program Memory Type
OTP
Eeprom Size
512 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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Pin Descriptions
2.13.3 Port C
Technical Data
42
While in single-chip operating modes, all port C pins are
general-purpose I/O pins. Port C inputs can be latched into an alternate
PORTCL register by providing an input transition to the STRA signal.
Port C can also be used in full handshake modes of parallel I/O where
the STRA input and STRB output act as handshake control lines.
When in expanded multiplexed modes, all port C pins are configured as
multiplexed address/data signals. During the address portion of each
MCU cycle, bits 7–0 of the address are output on the PC7–PC0 pins.
During the data portion of each MCU cycle (E high), PC7–PC0 are
bidirectional data signals, DATA7–DATA0. The direction of data at the
port C pins is indicated by the R/W signal.
The CWOM control bit in the PIOC register disables the port C P-channel
output driver. CWOM simultaneously affects all eight bits of port C.
Because the N-channel driver is not affected by CWOM, setting CWOM
causes port C to become an open-drain type output port suitable for
wired-OR operation.
It is customary to have an external pullup resistor on lines that are driven
by open-drain devices. Port C can only be configured for wired-OR
operation when the MCU is in single-chip mode. Refer to
Parallel Input/Output (I/O) Ports
functions.
In wired-OR mode:
When a port C bit is at logic level 0, it is driven low by the
N-channel driver.
When a port C bit is at logic level 1, the associated pin has
high-impedance, as neither the N-channel nor the P-channel
devices are active.
Pin Descriptions
for additional information about port C
M68HC11E Family — Rev. 3.2
Section 6.
MOTOROLA

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