MC68HC711E20CFN2 Freescale Semiconductor, MC68HC711E20CFN2 Datasheet - Page 58

• Manufacturer Part Number: MC68HC711E20CFN2
• Description: IC MCU 20K 2MHZ OTP 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711E20CFN2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Size: 20KB (20K x 8)
• Program Memory Type: OTP
• Eeprom Size: 512 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Central Processor Unit (CPU)
Technical Data
58
BRCLR(opr)
BRSET(opr)
BSET (opr)
CMPA (opr)
Mnemonic
BITA (opr)
BITB (opr)
CLR (opr)
BCS (rel)
BEQ (rel)
BGE (rel)
BGT (rel)
BHS (rel)
BNE (rel)
BRA (rel)
BRN (rel)
BSR (rel)
BVC (rel)
BLO (rel)
BVS (rel)
BLE (rel)
BLS (rel)
BLT (rel)
BMI (rel)
BPL (rel)
BHI (rel)
CLRA
CLRB
CBA
CLC
CLV
CLI
(msk)
(rel)
(msk)
(rel)
(msk)
Branch if = Zero
Branch if
Branch if > Zero
Higher or Same
Branch if
Branch if Lower
Branch if Lower
Branch if < Zero
Compare A to B
Branch if Minus
Branch if Carry
Branch Always
Overflow Clear
Clear Overflow
Branch if not =
Branch if Bit(s)
Clear Carry Bit
Clear Interrupt
Accumulator A
Accumulator B
Branch if Plus
Clear Memory
Compare A to
Branch Never
Overflow Set
Bit(s) Test A
with Memory
Bit(s) Test B
with Memory
Subroutine
Operation
Bit(s) Clear
Branch to
Set Bit(s)
Branch if
Branch if
Branch if
Branch if
Branch if
or Same
Memory
Higher
Mask
Clear
Clear
Zero
Byte
Flag
Set
Set
Zero
Zero
? Z + (N
? Z + (N
See Figure 3–2
? (M) • mm = 0
? M • mm = 0
M + mm
Description
? N
? N
? C + Z = 0
? C + Z = 1
? C = 1
? C = 0
? C = 1
? N = 1
? N = 0
? Z = 1
? Z = 0
? V = 0
? V = 1
? 1 = 1
? 1 = 0
0
0
0
0
0
A – M
A – B
A • M
B • M
0
Table 3-2. Instruction Set (Sheet 2 of 7)
V = 0
V = 1
C
M
A
B
V
I
V) = 0
V) = 1
M
A
A
A
A
A
B
B
B
B
B
A
B
A
A
A
A
A
Central Processor Unit (CPU)
Addressing
Mode
REL
REL
REL
REL
REL
REL
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
REL
REL
REL
REL
REL
REL
REL
REL
DIR
IND,X
IND,Y
REL
DIR
IND,X
IND,Y
DIR
IND,X
IND,Y
REL
REL
REL
INH
INH
INH
EXT
IND,X
IND,Y
INH
INH
INH
IMM
DIR
EXT
IND,X
IND,Y
18
18
18
18
18
18
18
Opcode
25
27
2C
2E
22
24
85
95
A5
A5
C5
D5
E5
E5
2F
25
23
2D
2B
26
2A
20
13
1F
1F
21
12
1E
1E
14
1C
1C
8D
28
29
11
0C
0E
7F
6F
6F
4F
5F
0A
81
91
A1
A1
B5
F5
B1
Instruction
rr
rr
rr
rr
rr
rr
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
rr
rr
rr
rr
rr
rr
rr
rr
dd mm rr
ff mm rr
ff mm rr
rr
dd mm rr
ff mm rr
ff mm rr
dd mm
ff mm
ff mm
rr
rr
rr
hh ll
ff
ff
ii
dd
hh ll
ff
ff
Operand
—
—
—
—
—
—
Cycles
3
3
3
3
3
3
2
3
4
4
5
2
3
4
4
5
3
3
3
3
3
6
7
8
6
7
8
6
7
8
6
3
3
2
2
2
6
6
7
2
2
2
2
3
4
4
5
3
3
3
3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
S
M68HC11E Family — Rev. 3.2
—
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—
—
—
—
—
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—
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—
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—
X
—
—
—
—
—
—
—
—
—
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—
—
—
—
—
—
—
—
—
—
—
—
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—
—
—
—
—
—
—
H
Condition Codes
—
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—
0
I
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
N
0
0
0
MOTOROLA
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Z
1
1
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
V
0
0
0
0
0
0
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
C
0
0
0
0