MC68HC711E20CFN2 Freescale Semiconductor, MC68HC711E20CFN2 Datasheet - Page 67

• Manufacturer Part Number: MC68HC711E20CFN2
• Description: IC MCU 20K 2MHZ OTP 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711E20CFN2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Size: 20KB (20K x 8)
• Program Memory Type: OTP
• Eeprom Size: 512 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

4.3.2 Expanded Mode
4.3.3 Test Mode
M68HC11E Family — Rev. 3.2
MOTOROLA
NOTE:
In expanded operating mode, the MCU can access the full 64-Kbyte
address space. The space includes:
The expansion bus is made up of ports B and C, and control signals AS
(address strobe) and R/W (read/write). R/W and AS allow the low-order
address and the 8-bit data bus to be multiplexed on the same pins.
During the first half of each bus cycle address information is present.
During the second half of each bus cycle the pins become the
bidirectional data bus. AS is an active-high latch enable signal for an
external address latch. Address information is allowed through the
transparent latch while AS is high and is latched when AS drives low.
The address, R/W, and AS signals are active and valid for all bus cycles,
including accesses to internal memory locations. The E clock is used to
enable external devices to drive data onto the internal data bus during
the second half of a read bus cycle (E clock high). R/W controls the
direction of data transfers. R/W drives low when data is being written to
the internal data bus. R/W will remain low during consecutive data bus
write cycles, such as when a double-byte store occurs.
Refer to
The write enable signal for an external memory is the NAND of the
E clock and the inverted R/W signal.
Test mode, a variation of the expanded mode, is primarily used during
Motorola’s internal production testing; however, it is accessible for
programming the configuration (CONFIG) register, programming
calibration data into electrically erasable, programmable read-only
memory (EEPROM), and supporting emulation and debugging during
development.
•
•
The same on-chip memory addresses used for single-chip mode
Addresses for external peripherals and memory devices
Operating Modes and On-Chip Memory
Figure
4-1.
Operating Modes and On-Chip Memory
Operating Modes
Technical Data
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