MC68HC711E20CFN2 Freescale Semiconductor, MC68HC711E20CFN2 Datasheet - Page 79

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MC68HC711E20CFN2

Manufacturer Part Number
MC68HC711E20CFN2
Description
IC MCU 20K 2MHZ OTP 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC711E20CFN2

Core Processor
HC11
Core Size
8-Bit
Speed
2MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Size
20KB (20K x 8)
Program Memory Type
OTP
Eeprom Size
512 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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M68HC11E Family — Rev. 3.2
MOTOROLA
1. Can be written only once in first 64 cycles out of reset in normal modes or at any time during special modes.
2. MC68HC711E9 only
3. MC68HC811E2 only
$103A
$103B
$103C
$103D
$103E
$1038
$1039
$103F
$103F
Addr.
System Configuration Register
System Configuration Register
Programming Control Register
System Configuration Options
Circuitry Register (COPRST)
Highest Priority I Bit Interrupt
and Miscellaneous Register
(PPROG)
EPROM and EEPROM
(HPRIO)
Arm/Reset COP Timer
RAM and I/O Mapping
Figure 4-7. Register and Control Bit Assignments (Sheet 8 of 8)
Register (OPTION)
Register Name
Register (INIT)
See page 111.
See page 91.
See page 95.
See page 83.
See page 89.
See page 87.
See page 87.
(CONFIG)
(CONFIG)
Reserved
Reserved
(3)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Operating Modes and On-Chip Memory
I = Indeterminate after reset
RBOOT
ADPU
RAM3
Bit 7
ODD
Bit 7
EE3
R
R
0
0
0
0
0
0
1
= Unimplemented
SMOD
EVEN
RAM2
CSEL
Bit 6
EE2
R
R
6
0
0
0
0
0
0
1
ELAT
IRQE
RAM1
MDA
Bit 5
EE1
R
R
5
0
0
0
0
0
0
1
(2)
(1)
IRV(NE)
DLY
RAM0
BYTE
Bit 4
EE0
R
R
R
4
1
0
0
0
0
0
1
(1)
Operating Modes and On-Chip Memory
= Reserved
NOSEC
NOSEC
PSEL3
REG3
ROW
CME
Bit 3
R
R
U
U
3
0
0
0
0
0
NOCOP ROMON
NOCOP
ERASE
PSEL2
REG2
U = Unaffected
Bit 2
R
R
U
U
2
0
0
0
1
0
EELAT
PSEL1
CR1
REG1
Bit 1
Technical Data
R
R
1
0
0
0
1
0
1
1
Memory Map
(1)
PSEL0
CR0
EPGM
EEON
EEON
REG0
Bit 0
Bit 0
R
R
U
0
0
0
0
1
1
(1)
79

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