MC68HC711E20CFN2 Freescale Semiconductor, MC68HC711E20CFN2 Datasheet - Page 119

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MC68HC711E20CFN2

Manufacturer Part Number
MC68HC711E20CFN2
Description
IC MCU 20K 2MHZ OTP 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC711E20CFN2

Core Processor
HC11
Core Size
8-Bit
Speed
2MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Size
20KB (20K x 8)
Program Memory Type
OTP
Eeprom Size
512 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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Chapter 8
Serial Peripheral Interface (SPI)
8.1 Introduction
The serial peripheral interface (SPI), an independent serial communications subsystem, allows the MCU
to communicate synchronously with peripheral devices, such as:
The SPI is also capable of inter-processor communication in a multiple master system. The SPI system
can be configured as either a master or a slave device. When configured as a master, data transfer rates
can be as high as one-half the E-clock rate (1.5 Mbits per second for a 3-MHz bus frequency). When
configured as a slave, data transfers can be as fast as the E-clock rate (3 Mbits per second for a 3-MHz
bus frequency).
8.2 Functional Description
The central element in the SPI system is the block containing the shift register and the read data buffer.
The system is single buffered in the transmit direction and double buffered in the receive direction. This
means that new data for transmission cannot be written to the shifter until the previous transfer is
complete; however, received data is transferred into a parallel read data buffer so the shifter is free to
accept a second serial character. As long as the first character is read out of the read data buffer before
the next serial character is ready to be transferred, no overrun condition occurs. A single MCU register
address is used for reading data from the read data buffer and for writing data to the shifter.
The SPI status block represents the SPI status functions (transfer complete, write collision, and mode
fault) performed by the serial peripheral status register (SPSR). The SPI control block represents those
functions that control the SPI system through the serial peripheral control register (SPCR).
Refer to
8.3 SPI Transfer Formats
During an SPI transfer, data is simultaneously transmitted and received. A serial clock line synchronizes
shifting and sampling of the information on the two serial data lines. A slave select line allows individual
selection of a slave SPI device; slave devices that are not selected do not interfere with SPI bus activities.
On a master SPI device, the select line can optionally be used to indicate a multiple master bus
contention. Refer to
Freescale Semiconductor
Frequency synthesizers
Liquid crystal display (LCD) drivers
Analog-to-digital (A/D) converter subsystems
Other microprocessors
Figure
8-1, which shows the SPI block diagram.
Figure
8-2.
M68HC11E Family Data Sheet, Rev. 5.1
119

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