MC68HC711E20CFN2 Freescale Semiconductor, MC68HC711E20CFN2 Datasheet - Page 131

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MC68HC711E20CFN2

Manufacturer Part Number
MC68HC711E20CFN2
Description
IC MCU 20K 2MHZ OTP 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC711E20CFN2

Core Processor
HC11
Core Size
8-Bit
Speed
2MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Size
20KB (20K x 8)
Program Memory Type
OTP
Eeprom Size
512 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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The control and status bits that implement the input capture functions are contained in:
To configure port A bit 3 as an input capture, clear the DDRA3 bit of the PACTL register. Note that this bit
is cleared out of reset. To enable PA3 as the fourth input capture, set the I4/O5 bit in the PACTL register.
Otherwise, PA3 is configured as a fifth output compare out of reset, with bit I4/O5 being cleared. If the
DDRA3 bit is set (configuring PA3 as an output), and IC4 is enabled, then writes to PA3 cause edges on
the pin to result in input captures. Writing to TI4/O5 has no effect when the TI4/O5 register is acting as IC4.
9.3.1 Timer Control Register 2
Use the control bits of this register to program input capture functions to detect a particular edge polarity
on the corresponding timer input pin. Each of the input capture functions can be independently configured
to detect rising edges only, falling edges only, any edge (rising or falling), or to disable the input capture
function. The input capture functions operate independently of each other and can capture the same
TCNT value if the input edges are detected within the same timer count cycle.
EDGxB and EDGxA — Input Capture Edge Control Bits
9.3.2 Timer Input Capture Registers
When an edge has been detected and synchronized, the 16-bit free-running counter value is transferred
into the input capture register pair as a single 16-bit parallel transfer. Timer counter value captures and
timer counter incrementing occur on opposite half-cycles of the phase 2 clock so that the count value is
stable whenever a capture occurs. The timer input capture registers are not affected by reset. Input
capture values can be read from a pair of 8-bit read-only registers. A read of the high-order byte of an
Freescale Semiconductor
There are four pairs of these bits. Each pair is cleared to 0 by reset and must be encoded to configure
the corresponding input capture edge detector circuit. IC4 functions only if the I4/O5 bit in the PACTL
register is set. Refer to
Pulse accumulator control register (PACTL)
Timer control 2 register (TCTL2)
Timer interrupt mask 1 register (TMSK1)
Timer interrupt flag 2 register (TFLG1)
Address:
Reset:
Read:
Write:
EDG4B
$1021
Bit 7
0
Table 9-2
EDGxB
Figure 9-3. Timer Control Register 2 (TCTL2)
0
0
1
1
Table 9-2. Timer Control Configuration
EDG4A
6
0
M68HC11E Family Data Sheet, Rev. 5.1
for timer control configuration.
EDGxA
EDG1B
5
0
0
1
0
1
EDG1A
Capture disabled
Capture on rising edges only
Capture on falling edges only
Capture on any edge
4
0
Configuration
EDG2B
3
0
EDG2A
2
0
EDG3B
1
0
EDG3A
Bit 0
0
Input Capture
131

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