MC68HC711E20CFN2 Freescale Semiconductor, MC68HC711E20CFN2 Datasheet - Page 141

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MC68HC711E20CFN2

Manufacturer Part Number
MC68HC711E20CFN2
Description
IC MCU 20K 2MHZ OTP 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC711E20CFN2

Core Processor
HC11
Core Size
8-Bit
Speed
2MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Size
20KB (20K x 8)
Program Memory Type
OTP
Eeprom Size
512 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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independent of the software latencies associated with flag clearing and service. For this reason, an RTI
period starts from the previous timeout, not from when RTIF is cleared.
Every timeout causes the RTIF bit in TFLG2 to be set, and if RTII is set, an interrupt request is generated.
After reset, one entire RTI period elapses before the RTIF is set for the first time. Refer to the
Interrupt Mask 2
Register.
9.5.1 Timer Interrupt Mask Register 2
This register contains the real-time interrupt enable bits.
TOI — Timer Overflow Interrupt Enable Bit
RTII — Real-Time Interrupt Enable Bit
PAOVI — Pulse Accumulator Overflow Interrupt Enable Bit
PAII — Pulse Accumulator Input Edge Bit
Bits [3:2] — Unimplemented
PR[1:0] — Timer Prescaler Select Bits
Freescale Semiconductor
Refer to
Refer to
Always read 0
Refer to
0 = TOF interrupts disabled
1 = Interrupt requested when TOF is set to 1
0 = RTIF interrupts disabled
1 = Interrupt requested when RTIF set to 1
9.7 Pulse
9.7 Pulse
Table
Address:
Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. Bits in TMSK2
enable the corresponding interrupt sources.
Reset:
Read:
Write:
Register,
9-4.
Accumulator.
Accumulator.
$1024
Figure 9-21. Timer Interrupt Mask 2 Register (TMSK2)
Bit 7
TOI
0
9.5.2 Timer Interrupt Flag Register
= Unimplemented
RTI
6
0
M68HC11E Family Data Sheet, Rev. 5.1
PAOVI
5
0
NOTE
PAII
4
0
3
0
2, and
9.5.3 Pulse Accumulator Control
2
0
PR1
1
0
Real-Time Interrupt (RTI)
Bit 0
PR0
0
9.4.9 Timer
141

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