MC68HC711E20CFN2 Freescale Semiconductor, MC68HC711E20CFN2 Datasheet - Page 37

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MC68HC711E20CFN2

Manufacturer Part Number
MC68HC711E20CFN2
Description
IC MCU 20K 2MHZ OTP 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC711E20CFN2

Core Processor
HC11
Core Size
8-Bit
Speed
2MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Size
20KB (20K x 8)
Program Memory Type
OTP
Eeprom Size
512 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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Freescale Semiconductor
1. SCP2 adds ÷39 to SCI prescaler and is present only in MC68HC(7)11E20.
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Addr.
Pulse Accumulator Control Regis-
Serial Communications Data Reg-
Serial Peripheral Control Register
Serial Peripheral Status Register
Serial Peripheral Data I/O Regis-
Pulse Accumulator Count Regis-
Analog-to-Digital Control Status
Serial Communications Control
Serial Communications Control
Serial Communications Status
Register Name
Timer Interrupt Flag 2
Register 1 (SCCR1)
Register 2 (SCCR2)
Baud Rate Register
Register (ADCTL)
Figure 2-7. Register and Control Bit Assignments (Sheet 4 of 6)
Register (SCSR)
See page 142.
See page 142.
See page 146.
See page 123.
See page 124.
See page 125.
See page 113.
See page 110.
See page 111.
See page 112.
See page 110.
See page 62.
ister (SCDR)
ter (PACNT)
ter (PACTL)
ter (SPDR)
(TFLG2)
(SPCR)
(BAUD)
(SPSR)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
M68HC11E Family Data Sheet, Rev. 5.1
I = Indeterminate after reset
DDRA7
TCLR
TDRE
R7/T7
Bit 7
CCF
SPIE
Bit 7
SPIF
TOF
Bit 7
TIE
R8
0
0
0
0
0
0
1
0
I
= Unimplemented
SCP2
WCOL
PAEN
R6/T6
Bit 6
RTIF
TCIE
SPE
Bit 6
TC
T8
6
0
0
0
0
0
0
1
0
I
(1)
PAMOD
PAOVF
DWOM
RDRF
SCAN
SCP1
R5/T5
Bit 5
Bit 5
RIE
5
0
0
0
0
0
0
0
0
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
PEDGE
MODF
MSTR
R4/T4
MULT
SCP0
Bit 4
PAIF
IDLE
Bit 4
ILIE
M
R
4
0
0
0
0
0
0
0
0
Indeterminate after reset
= Reserved
DDRA3
WAKE
CPOL
RCKB
R3/T3
Bit 3
Bit 3
OR
CD
TE
3
0
0
0
0
0
0
0
0
CPHA
U = Unaffected
SCR2
R2/T2
I4/O5
Bit 2
Bit 2
RE
NF
CC
U
2
0
0
1
0
0
0
0
R1/T1
RTR1
SPR1
SCR1
Bit 1
RWU
Bit 1
FE
CB
U
U
1
0
0
0
0
0
0
Memory Map
SCR0
R0/T0
RTR0
SPR0
Bit 0
Bit 0
Bit 0
SBK
CA
U
U
0
0
0
0
0
0
37

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