MC68HC711E20CFN2 Freescale Semiconductor, MC68HC711E20CFN2 Datasheet - Page 60

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MC68HC711E20CFN2

Manufacturer Part Number
MC68HC711E20CFN2
Description
IC MCU 20K 2MHZ OTP 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC711E20CFN2

Core Processor
HC11
Core Size
8-Bit
Speed
2MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Size
20KB (20K x 8)
Program Memory Type
OTP
Eeprom Size
512 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Analog-to-Digital (A/D) Converter
3.3 A/D Converter Power-Up and Clock Select
Bit 7 of the OPTION register controls A/D converter power-up. Clearing ADPU removes power from and
disables the A/D converter system. Setting ADPU enables the A/D converter system. Stabilization of the
analog bias voltages requires a delay of as much as 100 µs after turning on the A/D converter. When the
A/D converter system is operating with the MCU E clock, all switching and comparator operations are
inherently synchronized to the main MCU clocks. This allows the comparator output to be sampled at
relatively quiet times during MCU clock cycles. Since the internal RC oscillator is asynchronous to the
MCU clock, there is more error attributable to internal system clock noise. A/D converter accuracy is
reduced slightly while the internal RC oscillator is being used (CSEL = 1).
ADPU — A/D Power-Up Bit
CSEL — Clock Select Bit
IRQE — Configure IRQ for Edge-Sensitive Only Operation
DLY — Enable Oscillator Startup Delay Bit
CME — Clock Monitor Enable Bit
Bit 2 — Not implemented
CR[1:0] — COP Timer Rate Select Bits
60
Refer to
Refer to
Always reads 0
Refer to
0 = A/D powered down
1 = A/D powered up
0 = A/D and EEPROM use system E clock.
1 = A/D and EEPROM use internal RC clock.
0 = The oscillator startup delay coming out of stop is bypassed and the MCU resumes processing
1 = A delay of approximately 4000 E-clock cycles is imposed as the MCU is started up from the stop
within about four bus cycles.
power-saving mode. This delay allows the crystal oscillator to stabilize.
Chapter 5 Resets and
Chapter 5 Resets and
Chapter 5 Resets and Interrupts
1. Can be written only once in first 64 cycles out of reset in normal modes or at any time in special modes
Address: $1039
Reset:
Read:
Write:
Figure 3-4. System Configuration Options Register (OPTION)
ADPU
Bit 7
0
= Unimplemented
CSEL
6
0
Interrupts.
Interrupts.
M68HC11E Family Data Sheet, Rev. 5.1
IRQE
5
0
(1)
and
Chapter 9 Timing
DLY
4
1
(1)
CME
3
0
Systems.
2
0
CR1
1
0
(1)
Freescale Semiconductor
CR0
Bit 0
0
(1)

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