MC68HC711E20CFN2 Freescale Semiconductor, MC68HC711E20CFN2 Datasheet - Page 90
Manufacturer Part Number
IC MCU 20K 2MHZ OTP 52-PLCC
Specifications of MC68HC711E20CFN2
Number Of I /o
Program Memory Size
20KB (20K x 8)
Program Memory Type
512 x 8
768 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
-40°C ~ 85°C
Package / Case
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Resets and Interrupts
5.5.4 Software Interrupt (SWI)
SWI is an instruction, and thus cannot be interrupted until complete. SWI is not inhibited by the global
mask bits in the CCR. Because execution of SWI sets the I mask bit, once an SWI interrupt begins, other
interrupts are inhibited until SWI is complete, or until user software clears the I bit in the CCR.
5.5.5 Maskable Interrupts
The maskable interrupt structure of the MCU can be extended to include additional external interrupt
sources through the IRQ pin. The default configuration of this pin is a low-level sensitive wired-OR
network. When an event triggers an interrupt, a software accessible interrupt flag is set. When enabled,
this flag causes a constant request for interrupt service. After the flag is cleared, the service request is
5.5.6 Reset and Interrupt Processing
illustrate the reset and interrupt process.
illustrates how the CPU
begins from a reset and how interrupt detection relates to normal opcode fetches.
expansion of a block in
and illustrates interrupt priorities.
shows the resolution of
interrupt sources within the SCI subsystem.
5.6 Low-Power Operation
Both stop mode and wait mode suspend CPU operation until a reset or interrupt occurs. Wait mode
suspends processing and reduces power consumption to an intermediate level. Stop mode turns off all
on-chip clocks and reduces power consumption to an absolute minimum while retaining the contents of
the entire RAM array.
5.6.1 Wait Mode
The WAI opcode places the MCU in wait mode, during which the CPU registers are stacked and CPU
processing is suspended until a qualified interrupt is detected. The interrupt can be an external IRQ, an
XIRQ, or any of the internally generated interrupts, such as the timer or serial interrupts. The on-chip
crystal oscillator remains active throughout the wait standby period.
The reduction of power in the wait condition depends on how many internal clock signals driving on-chip
peripheral functions can be shut down. The CPU is always shut down during wait. While in the wait state,
the address/data bus repeatedly runs read cycles to the address where the CCR contents were stacked.
The MCU leaves the wait state when it senses any interrupt that has not been masked.
The free-running timer system is shut down only if the I bit is set to 1 and the COP system is disabled by
NOCOP being set to 1. Several other systems also can be in a reduced power-consumption state
depending on the state of software-controlled configuration control bits. Power consumption by the
analog-to-digital (A/D) converter is not affected significantly by the wait condition. However, the A/D
converter current can be eliminated by writing the ADPU bit to 0. The SPI system is enabled or disabled
by the SPE control bit. The SCI transmitter is enabled or disabled by the TE bit, and the SCI receiver is
enabled or disabled by the RE bit. Therefore, the power consumption in wait is dependent on the
M68HC11E Family Data Sheet, Rev. 5.1