MC68HC711E20CFN2 Freescale Semiconductor, MC68HC711E20CFN2 Datasheet - Page 99

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MC68HC711E20CFN2

Manufacturer Part Number
MC68HC711E20CFN2
Description
IC MCU 20K 2MHZ OTP 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC711E20CFN2

Core Processor
HC11
Core Size
8-Bit
Speed
2MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Size
20KB (20K x 8)
Program Memory Type
OTP
Eeprom Size
512 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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6.3 Port B
In single-chip or bootstrap modes, port B pins are general-purpose outputs. In expanded or special test
modes, port B pins are high-order address outputs.
6.4 Port C
In single-chip and bootstrap modes, port C pins reset to high-impedance inputs. (DDRC bits are set to 0.)
In expanded and special test modes, port C pins are multiplexed address/data bus and the port C register
address is treated as an external memory location.
Freescale Semiconductor
Single-chip or bootstrap modes:
Expanded or special test modes:
Single-chip or bootstrap modes:
Expanded or special test modes:
Address:
Address:
Address:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
ADDR15
ADDR7
DATA7
$1004
$1003
$1005
PCL7
Bit 7
PB7
Bit 7
PC7
Bit 7
0
0
Figure 6-5. Port C Latched Register (PORTCL)
Figure 6-3. Port B Data Register (PORTB)
Figure 6-4. Port C Data Register (PORTC)
ADDR14
ADDR6
DATA6
PCL6
PB6
PC6
6
0
0
6
6
M68HC11E Family Data Sheet, Rev. 5.1
ADDR13
ADDR5
DATA5
PCL5
PB5
PC5
5
0
0
5
5
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
ADDR12
ADDR4
DATA4
PCL4
PB4
PC4
4
0
0
4
4
ADDR11
ADDR3
DATA3
PCL3
PB3
PC3
3
0
0
3
3
ADDR10
ADDR2
DATA2
PCL2
PB2
PC2
2
0
0
2
2
ADDR9
ADDR1
DATA1
PCL1
PC1
PB1
1
0
0
1
1
ADDR8
ADDR0
DATA0
PCL0
Bit 0
Bit 0
PC0
Bit 0
PB0
0
0
Port B
99

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