MC68HC908QY2CP Freescale Semiconductor, MC68HC908QY2CP Datasheet - Page 130

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MC68HC908QY2CP

Manufacturer Part Number
MC68HC908QY2CP
Description
IC MCU 1.5K FLASH W/ADC 16-DIP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC68HC908QY2CP

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Peripherals
LVD, POR, PWM
Number Of I /o
13
Program Memory Size
1.5KB (1.5K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
16-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Connectivity
-

Available stocks

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Quantity
Price
Part Number:
MC68HC908QY2CPE
Manufacturer:
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Quantity:
7 762
Timer Interface Module (TIM)
CHxF — Channel x Flag Bit
CHxIE — Channel x Interrupt Enable Bit
MSxB — Mode Select Bit B
MSxA — Mode Select Bit A
130
When channel x is an input capture channel, this read/write bit is set when an active edge occurs on
the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the
TIM counter registers matches the value in the TIM channel x registers.
Clear CHxF by reading the TIM channel x status and control register with CHxF set and then writing
a 0 to CHxF. If another interrupt request occurs before the clearing sequence is complete, then writing
a 0 to CHxF has no effect. Therefore, an interrupt request cannot be lost due to inadvertent clearing
of CHxF.
Reset clears the CHxF bit. Writing a 1 to CHxF has no effect.
This read/write bit enables TIM CPU interrupt service requests on channel x. Reset clears the CHxIE
bit.
This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIM
channel 0 status and control register.
Setting MS0B disables the channel 1 status and control register and reverts TCH1 to general-purpose
I/O.
Reset clears the MSxB bit.
When ELSxB:A ≠ 00, this read/write bit selects either input capture operation or unbuffered output
compare/PWM operation. See
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
Address: $0025
Address: $0028
Reset:
Reset:
Read:
Read:
Write:
Write:
CH0F
CH1F
Bit 7
Bit 7
0
0
0
0
Figure 14-7. TIM Channel Status and Control
TSC0
TSC1
= Unimplemented
CH0IE
CH1IE
MC68HC908QY/QT Family Data Sheet, Rev. 6
6
0
6
0
Table
Registers (TSC0:TSC1)
14-3.
MS0B
5
0
5
0
0
MS0A
MS1A
4
0
4
0
ELS0B
ELS1B
3
0
3
0
ELS0A
ELS1A
2
0
2
0
TOV0
TOV1
1
0
1
0
Freescale Semiconductor
CH0MAX
CH1MAX
Bit 0
Bit 0
0
0

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