MC68HC908QY2CDW Freescale Semiconductor, MC68HC908QY2CDW Datasheet - Page 135

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MC68HC908QY2CDW

Manufacturer Part Number
MC68HC908QY2CDW
Description
IC MCU 1.5K FLASH W/ADC 16-SOIC
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC68HC908QY2CDW

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Peripherals
LVD, POR, PWM
Number Of I /o
13
Program Memory Size
1.5KB (1.5K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
16-SOIC (0.300", 7.5mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Connectivity
-
When the internal address bus matches the value written in the break address registers or when software
writes a 1 to the BRKA bit in the break status and control register, the CPU starts a break interrupt by:
The break interrupt timing is:
By updating a break address and clearing the BRKA bit in a break interrupt routine, a break interrupt can
be generated continuously.
15.2.1.1 Flag Protection During Break Interrupts
The system integration module (SIM) controls whether or not module status bits can be cleared during
the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status
bits during the break state. See
for each module.
15.2.1.2 TIM During Break Interrupts
A break interrupt stops the timer counter.
15.2.1.3 COP During Break Interrupts
The COP is disabled during a break interrupt with monitor mode when BDCOP bit is set in break auxiliary
register (BRKAR).
15.2.2 Break Module Registers
These registers control and monitor operation of the break module:
Freescale Semiconductor
Loading the instruction register with the SWI instruction
Loading the program counter with $FFFC and $FFFD ($FEFC and $FEFD in monitor mode)
When a break address is placed at the address of the instruction opcode, the instruction is not
executed until after completion of the break interrupt routine.
When a break address is placed at an address of an instruction operand, the instruction is executed
before the break interrupt.
When software writes a 1 to the BRKA bit, the break interrupt occurs just before the next instruction
is executed.
Break status and control register (BRKSCR)
Break address register high (BRKH)
Break address register low (BRKL)
Break status register (BSR)
Break flag control register (BFCR)
A break address should be placed at the address of the instruction opcode.
When software does not change the break address and clears the BRKA
bit in the first break interrupt routine, the next break interrupt will not be
generated after exiting the interrupt routine even when the internal address
bus matches the value written in the break address registers.
13.8.2 Break Flag Control Register
MC68HC908QY/QT Family Data Sheet, Rev. 6
CAUTION
and the Break Interrupts subsection
Break Module (BRK)
135

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